3V 64M-BIT SERIAL FLASH MEMORY WITH …

1 W25Q64FV Publication Release Date: July 18, 2017 - 1 Revision S 3V 64M-BIT SERIAL FLASH MEMORY with DUAL/QUAD SPI & QPI W25Q64FV - 2 - Table of Contents 1. GENERAL DESCRIPTION .. 5 2. FEATURES .. 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS .. 6 Pin Configuration SOIC / VSOP 208-mil .. 6 Pad Configuration WSON 6x5-mm / 8X6-mm, XSON 4x4-mm .. 6 Pin Configuration PDIP 300-mil .. 7 Pin Description SOIC/VSOP 208-mil, WSON 6x5/8x6-mm, XSON 4x4-mm and PDIP 300-mil 7 Pin Configuration SOIC 300-mil .. 8 Pin Description SOIC 300-mil.

2 8 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) .. 9 Ball Description TFBGA 8x6-mm .. 9 Ball Configuration WLCSP .. 10 Ball Description WLCSP .. 10 4. PIN DESCRIPTIONS .. 11 Chip Select (/CS) .. 11 SERIAL Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .. 11 Write Protect (/WP) .. 11 HOLD (/HOLD) .. 11 SERIAL Clock (CLK) .. 11 5. BLOCK DIAGRAM .. 12 6. FUNCTIONAL DESCRIPTIONS .. 13 SPI/QPI OPERATIONS .. 13 Standard SPI Instructions .. 13 Dual SPI Instructions .. 13 Quad SPI Instructions .. 14 QPI Instructions .. 14 Hold Function.

3 14 WRITE PROTECTION .. 15 Write Protect Features .. 15 7. STATUS REGISTERS AND INSTRUCTIONS .. 16 STATUS REGISTERS .. 16 BUSY .. 16 Write Enable Latch (WEL) .. 16 Block Protect Bits (BP2, BP1, BP0) .. 16 Top/Bottom Block Protect (TB) .. 16 Sector/Block Protect (SEC) .. 16 W25Q64FV Publication Release Date: July 18, 2017 - 3 - Revision S Complement Protect (CMP) .. 16 Status Register Protect (SRP1, SRP0) .. 17 Erase/Program Suspend Status (SUS) .. 17 Security Register Lock Bits (LB3, LB2, LB1) .. 17 Quad Enable (QE).

4 17 W25Q64FV Status Register MEMORY Protection (CMP = 0) .. 19 W25Q64FV Status Register MEMORY Protection (CMP = 1) .. 20 INSTRUCTIONS .. 21 Manufacturer and Device Identification .. 21 Instruction Set Table 1 (Standard SPI Instructions)(1).. 22 Instruction Set Table 2 (Dual SPI Instructions) .. 23 Instruction Set Table 3 (Quad SPI Instructions) .. 23 Instruction Set Table 4 (QPI Instructions)(14) .. 24 Write Enable (06h) .. 26 Write Enable for Volatile Status Register (50h) .. 26 Write Disable (04h) .. 27 Read Status Register-1 (05h) and Read Status Register-2 (35h).

5 27 Write Status Register (01h) .. 28 Read Data (03h) .. 30 Fast Read (0Bh) .. 31 Fast Read Dual Output (3Bh) .. 33 Fast Read Quad Output (6Bh) .. 34 Fast Read Dual I/O (BBh) .. 35 Fast Read Quad I/O (EBh) .. 37 Word Read Quad I/O (E7h) .. 40 Octal Word Read Quad I/O (E3h) .. 42 Set Burst with Wrap (77h) .. 44 Page Program (02h) .. 45 Quad Input Page Program (32h) .. 47 Sector Erase (20h) .. 48 32KB Block Erase (52h) .. 49 64KB Block Erase (D8h) .. 50 Chip Erase (C7h / 60h) .. 51 Erase / Program Suspend (75h) .. 52 Erase / Program Resume (7Ah).

6 54 Power-down (B9h) .. 55 Release Power-down / Device ID (ABh) .. 56 Read Manufacturer / Device ID (90h) .. 58 Read Manufacturer / Device ID Dual I/O (92h) .. 59 Read Manufacturer / Device ID Quad I/O (94h) .. 60 Read Unique ID Number (4Bh).. 61 W25Q64FV - 4 - Read JEDEC ID (9Fh) .. 62 Read SFDP Register (5Ah) .. 63 Erase Security Registers (44h) .. 64 Program Security Registers (42h) .. 65 Read Security Registers (48h) .. 66 Set Read Parameters (C0h) .. 67 Burst Read with Wrap (0Ch) .. 68 Enable QPI (38h) .. 69 Disable QPI (FFh) .. 70 Enable Reset (66h) and Reset (99h).

7 71 8. ELECTRICAL CHARACTERISTICS .. 72 Absolute Maximum Ratings (1)(2) .. 72 Operating 72 Power-up Power-down Timing and Requirements(1) .. 73 DC Electrical Characteristics .. 74 AC Measurement Conditions(1) .. 75 AC Electrical Characteristics .. 76 AC Electrical Characteristics (cont d) .. 77 SERIAL Output Timing .. 78 SERIAL Input Timing .. 78 /HOLD Timing .. 78 /WP Timing .. 78 9. PACKAGE SPECIFICATION .. 79 8-Pin SOIC 208-mil (Package Code SS) .. 79 8-Pin VSOP 208-mil (Package Code ST) .. 80 8-Pin PDIP 300-mil (Package Code DA) .. 81 8-Pad WSON 6x5-mm (Package Code ZP).

8 82 8-Pad WSON 8x6-mm (Package Code ZE) .. 83 8-Pad XSON (Package Code XG) .. 84 16-Pin SOIC 300-mil (Package Code SF) .. 85 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) .. 86 24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) .. 87 16-Ball WLCSP (Package Code BY) .. 88 Ordering Information .. 89 Valid Part Numbers and Top Side Marking .. 90 10. REVISION HISTORY .. 91 W25Q64FV Publication Release Date: July 18, 2017 - 5 - Revision S 1. GENERAL DESCRIPTION The W25Q64FV ( 64M-BIT ) SERIAL FLASH MEMORY provides a storage solution for systems with limited space, pins and power.

9 The 25Q series offers flexibility and performance well beyond ordinary SERIAL FLASH devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single to power supply with current consumption as low as 4mA active and 1 A for power-down. All devices are offered in space-saving packages. The W25Q64FV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase).

10 The W25Q64FV has 2,048 erasable sectors and 128 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.) The W25Q64FV support the standard SERIAL Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface (QPI): SERIAL Clock, Chip Select, SERIAL Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104 MHz are supported allowing equivalent clock rates of 208 MHz (104 MHz x 2) for Dual I/O and 416 MHz (104 MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O and QPI instructions.