4Gb E-die DDR3L SDRAM Only x16 - Samsung US | Mobile

1 Rev. , Jun. 2016. K4B4G1646E. 4Gb E-die DDR3L SDRAM Only x16. 96 FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet Samsung ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND. SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise.

2 Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. 2016 Samsung Electronics Co., Ltd. All rights reserved. -1- Rev. K4B4G1646E datasheet DDR3L SDRAM .

3 Revision History Revision No. History Draft Date Remark Editor - First SPEC Release Dec. 2014 - - Addition of information about I-temp 23th Jun. 2016 - -2- Rev. K4B4G1646E datasheet DDR3L SDRAM . Table Of Contents 4Gb E-die DDR3L SDRAM Olny x16. 1. Ordering Information .. 5. 2. Key 5. 3. Package pinout/Mechanical Dimension & 6. x16 Package Pinout (Top view) : 96ball FBGA Package .. 6. FBGA Package Dimension (x16).. 7. 4. Input/Output Functional 8. 5. DDR3 SDRAM Addressing .. 9. 6. Absolute Maximum Ratings .. 10. Absolute Maximum DC 10. DRAM Component Operating Temperature Range .. 10.

4 7. AC & DC Operating 10. Recommended DC operating Conditions .. 10. 8. AC & DC Input Measurement Levels .. 11. AC & DC Logic input levels for single-ended signals .. 11. VREF Tolerances .. 13. AC & DC Logic Input Levels for Differential Signals .. 14. Differential signals definition .. 14. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .. 14. Single-ended requirements for differential signals .. 15. Differential Input Cross Point 17. Slew rate definition for Differential Input Signals .. 17. Slew rate definitions for Differential Input Signals .. 18. 9. AC & DC Output Measurement Levels.

5 18. Single-ended AC & DC Output 18. Differential AC & DC Output 18. Single-ended Output Slew Rate .. 19. Differential Output Slew Rate .. 20. Reference Load for AC Timing and Output Slew Rate .. 20. Overshoot/Undershoot Specification .. 21. Address and Control Overshoot and Undershoot 21. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications .. 22. 34ohm Output Driver DC Electrical 23. Output Drive Temperature and Voltage Sensitivity .. 25. On-Die Termination (ODT) Levels and I-V Characteristics .. 25. ODT DC Electrical Characteristics .. 26. ODT Temperature and Voltage sensitivity.

6 28. ODT Timing Definitions .. 29. Test Load for ODT Timings .. 29. ODT Timing Definitions .. 29. 10. IDD Current Measure Method .. 32. IDD Measurement Conditions .. 32. 11. 4Gb DDR3L SDRAM E-die IDD Specification Table .. 41. 12. Input/Output Capacitance .. 42. 13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 .. 43. Clock Specification .. 43. Definition for tCK(avg).. 43. Definition for tCK(abs).. 43. Definition for tCH(avg) and tCL(avg) .. 43. Definition for note for tJIT(per), tJIT(per, Ick) .. 43. Definition for tJIT(cc), tJIT(cc, Ick) .. 43. Definition for tERR(nper).

7 43. Refresh Parameters by Device 44. Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin .. 44. -3- Rev. K4B4G1646E datasheet DDR3L SDRAM . Speed Bin Table Notes .. 48. 14. Timing Parameters by Speed Grade .. 49. Jitter Notes .. 53. Timing Parameter 54. Address/Command Setup, Hold and Derating : .. 55. Data Setup, Hold and Slew Rate Derating : .. 64. -4- Rev. K4B4G1646E datasheet DDR3L SDRAM . 1. Ordering Information [ Table 1 ] Samsung 4Gb DDR3L E-die ordering information table Organization DDR3L -1600 (11-11-11) DDR3L -1866 (13-13-13)3 Package 256Mx16 K4B4G1646E-BYK0 K4B4G1646E-BYMA 96 FBGA.

8 256Mx16 K4B4G1646E-BMK0 K4B4G1646E-BMMA 96 FBGA. NOTE : 1. Speed bin is in order of CL-tRCD-tRP. 2. 13th digit stands for below. "Y" : Commercial temp/Normal power "M" : Industrial temp/Normal power 3. Backward compatible to DDR3L -1600(11-11-11), DDR3L -1333(9-9-9). 2. Key Features [ Table 2 ] 4Gb DDR3 E-die Speed bins DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866. Speed Unit 6-6-6 7-7-7 9-9-9 11-11-11 13-13-13. tCK(min) ns CAS Latency 6 7 9 11 13 nCK. tRCD(min) 15 ns tRP(min) 15 ns tRAS(min) 36 35 34 ns tRC(min) ns JEDEC standard ( ~ ) & ( ~ ) The 4Gb DDR3 SDRAM E-die is organized as a 32 Mbit x 16I/Os x 8banks, VDDQ = ( ~ ) & ( ~ ) device.

9 This synchronous device achieves high speed double-data-rate 400 MHz fCK for 800Mb/sec/pin, 533 MHz fCK for 1066Mb/sec/pin, transfer rates of up to 1866Mb/sec/pin (DDR3-1866) for general applica- 667 MHz fCK for 1333Mb/sec/pin, 800 MHz fCK for 1600Mb/sec/pin tions. 933 MHz fCK for 1866Mb/sec/pin The chip is designed to comply with the following key DDR3 SDRAM fea- 8 Banks tures such as posted CAS, Programmable CWL, Internal (Self) Calibration, Programmable CAS Latency(posted CAS): 5,6,7,8,9,10,11,12,13 On Die Termination using ODT pin and Asynchronous Reset . Programmable Additive Latency: 0, CL-2 or CL-1 clock All of the control and address inputs are synchronized with a pair of exter- Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 nally supplied differential clocks.

10 Inputs are latched at the crosspoint of dif- (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9(DDR3-1866) ferential clocks (CK rising and CK falling). All I/Os are synchronized with a 8-bit pre-fetch pair of bidirectional strobes (DQS and DQS) in a source synchronous fash- Burst Length: 8 , 4 with tCCD = 4 which does not allow seamless read ion. The address bus is used to convey row, column, and bank address or write [either On the fly using A12 or MRS]. information in a RAS/CAS multiplexing style. The DDR3 device operates Bi-directional Differential Data-Strobe with a single ( ~ ) or ( ~ ) power supply Internal(self) calibration : Internal self calibration through ZQ pin and ( ~ ) or ( ~ ) VDDQ.