제5장 PLD의 이해와 실습 - mmlab.snu.ac.kr

1 2006 1 5 PLD - PAL PLA, EPROM, CPLD . - MAX PLUS II CPLD . - CPLD . - VHDL . 1. PLD(Programmable Logic Device) PLD program IC . PLD . A. PROM(Promgrammable Read Only Memory) (AND ) (Memory array) (OR ) . B. PLA(Programmable Logic Array) PLA AND OR PROM AND , OR . SOP(Sum of Product) . delay.

2 C. PAL(Programmable Array Logic) PAL PLA . PAL AND , OR . , . D. SPLD(Simple Programmable Logic Device) PAL 200 . E. CPLD(Complex Programmable Logic Device) CPLD Altera . Embedded Array Block . CPLD 2006 1 . F. FPGA(Field Programmable Gate Array) FPGA CPLD PLD Array Row . SPLD segmented interconnect.

3 CPLD . CPLD . 2. MAX PLUS II CPLD program MAX PLUS II 2:1 MUX schematic CPLD file . < > MUX(Multiplexer) 2n n bit selector . , 4:1 MUX 2 bit selector 4 1 . 4:1 MUX . I3I2I1I0S1S0 Out X X X X 0 0 I0X X X X 0 1 I1X X X X 1 0 I2X X X X 1 1 I3 4-1. 4:1 MUX 1. Selector 0 ( 00 ) , 1 ( 01 ) , 2 ( 10 ) , 3 ( 11 ).

4 MUX Max+plus II . (MUX 5 .) 1) MAX PLUS II . ( schematic graphic editor file(.gdf) . 2006 1 [ 5-1] .gdf file 2) Symbol Enter Symbol ( schematic ) MUX . [ 5-2] 2006 1 2:1 MUX input I1, I0, Selector S, Output O O = S *I0 + S*I1 . and, or, inverter gate . [ 5-3] 2:1 MUX schematic 3) Assign Device Device family MAX7000S Devices EPM7064 SLC44-5 . [ 5-4] device ( CPLD.

5 4) File File Project->Set Project to Current File Project 2006 1 [ 5-5] schematic 5) MAX+plus II Compiler compile . ( .pof file WACCESS CPLD .) [ 5-6] MAX+plus II compiler start click compile . 2006 1 [ 5-7] error compile schematic compile . [ 5-8] .pof file 2006 1 CPLD .pof . 6) pin ( , ) pin . Assign Pin/ . [ 5-9] Pin assign Search click.

6 [ 5-10] Node Data Base 2006 1 List click schematic port . port 5-5 5-5 Pin Pin . (Pin VCC, GND available port ) Pin assign . [ 5-11] Pin schematic CPLD Pin . [ 5-12] Pin assign schematic 2006 1 Pin assign . 7) MAX+plus II Waveform editor . ( schematic debugging compile .) 1 Waveform editor input, output pin , wave.

7 (1 ) [ 5-13] waveform editor S 200ns, I0 400ns, I1 800ns . [ 5-14] simulator 2006 1 simulator . Start click . [ 5-15] simulator error . 5-11 Open SCF click . [ 5-16] MUX . 3. CPLD programmable logic MAX+plus II CPLD download .. ALL-11 (serial port PC chip ) kit WACCESS CPLD . WACCESS . 2006 1 [ 5-17] ALL-11 main Device vendor chip.

8 Altera EPM7064 SLC CPLD . [ 5-18] vendor Altera Altera CPLD . MAX7000S EPM7064 SLC44 . 2006 1 [ 5-19] CPLD CPLD . [ 5-20] CPLD .pof load . File Load POF_FILE to programmer buffer .pof file load . 2006 1 File load 5-20 Program program . [ 5-21] program Run click CPLD . 4. VHDL overview z VHDL design unit VHDL design unit . Entity unit : interface Architecture body unit : Configuration unit : entity unit architecture body unit Package unit : design unit Package body unit : package unit function procedure Entity Architecture.

9 Z VHDL library VHDL IEEE library library IEEE; 2006 1 . library . std_logic_1164 (std_logic types & related function) std_logic_arith (arithmetic function) std_logic_signed (signed arithmetic functions) std_logic_unsigned (unsigned arithmetic functions) use library . ( use ; ) z Entity Arichitecture Entity design component interface . architecture body . Arichitecture Entity . VHDL . 2006 1 [ 5-22] VHDL generics.

10 Generics(constant tplh, tphl : time := 5ns; tphz, tplz : time := 3ns; default_value : integer :=1; ); port interface . ) port ( a : in std_logic; b : in std_logic; c : out std_logic ); VHDL . , VHDL code . VHDL reference . ( ) z Process statement Architecture begin end process concurrent .. architecture body . Process . , architecture body process process process.