8. 조합논리회로설계 한동일 - dasan.sejong.ac.kr

1 vhdl vhdl 8.. 2/37 . (test bench) (test bench) (t t b h) ? (test bench) ? , , , vhdl vhdl : vhdl : vhdl vhdl vhdl vhdl 3/37 vhdl AND AND AYBY AND vhdl entityand_gate isport (A, B : inbit; Y : outbit);end;architectureand_gate ofand_gate isbeginY <= A andB ;4/37end; AND AND ABY=A and BABY=A and B000A010100B11110 ns 20 ns 30 ns 40 ns vhdl A <= '0', '1' after20 ns, '0' after40 ns;B<='0''1'after10 ns'0'after20 ns'1'after30 ns'0'after40 ns;5/37B < 0, 1 after10 ns, 0 after20 ns, 1 after30 ns, 0 after40 ns.

2 Vs. : vhdl : vhdl 6/37 AND AND entitytb_AND_gate isport(Y : outbit) ;endtb_AND_gate ;architecturesimulation oftb_AND_gate iscomponentAND_gate t(A Bibit Ytbit)port(A, B: inbit; Y : outbit);end component;signala b : bit;signala,b : bit;begina <= '0', '1' after20 ns, '0' after40 ns; ,,;b <= '0', '1' after10 ns, '0' after20 ns, '1' after30 ns, '0' after40 ns;U0 : AND_gate port map (A=>a, B=>b, Y=>Y);7/37end; 8/37 (ltil ) (multiplexer)9/37 vhdl vhdl entitymux_4x1 isport(a, b, c, d: inbit.)

3 Sel : inbit_vector(1 downto0);q : outbit);end;architecturewith_select ofmux_4x1 isbibeginwithsel selectq<=awhen"00"q < a when00,b when"01",c when"10",,d when"11",a when others;10/37end; entitytb_mux_4x1 isendtb mux 4x1 ;endtb_mux_4x1 ;architecturesimulation oftb_mux_4x1 iscomponentmux_4x1 port(a, b, c, d: inbit; sel : inbit_vector(1 downto0);q : outbit);end component;p;signala,b,c,d : bit; signalsel : bit_vector(1 downto0);beginA<='0''1'after20 ns'0'after40 ns;A <= 0, 1 after20 ns, 0 after40 ns; B <= '0', '1' after10 ns, '0' after20 ns, '1' after30 ns, '0' after40 ns;C <= '0', '1' after40 ns, '0' after80 ns;D <= '0', '1' after20 ns, '0' after40 ns, '1' after60 ns, '0' after80 ns;SEL <= "00", "01" after20 ns, "10" after40 ns, "11" after60 ns, "00" after80 ns;U0 : mux 4x1port map(A=>A,B=>B,C=>C, D=>D, SEL=>SEL, Q=>open);11/37U0 : mux_4x1 port map (AA,BB,CC, DD, SEL SEL, Qopen);end; 12/37 entitytb_mux_4x1 isendtb mux 4x1 ;endtb_mux_4x1 ;architecturesimulation oftb_mux_4x1 iscomponentmux_4x1 port(a, b, c, d: inbit; sel : inbit_vector(1 downto0);q : outbit);end component;p;signala,b,c,d : bit; signalsel : bit_vector(1 downto0);beginA<='0''1'after5ns'0'after1 0 ns'1'after15 ns'0'after20 ns'1'after80 ns;A <= 0, 1 after5 ns, 0 after10 ns, 1 after15 ns, 0 after20 ns, 1 after80 ns.

4 B <= '0', '1' after10 ns, '0' after20 ns, '1' after30 ns, '0' after40 ns;C <= '0', '1' after15 ns, '0' after30 ns, '1' after45 ns, '0' after60 ns;D <= '0', '1' after20 ns, '0' after40 ns, '1' after60 ns, '0' after70 ns;SEL <= "00", "01" after20 ns, "10" after40 ns, "11" after60 ns, "00" after80 ns;U0 : mux 4x1port map(A=>A,B=>B,C=>C, D=>D, SEL=>SEL, Q=>open);13/37U0 : mux_4x1 port map (AA,BB,CC, DD, SEL SEL, Qopen);end; 14/37 (t) (comparator)ABYAY ABY00 1010B01010 0(A=B) 11 115/37 vhdl vhdl entitycomparator isport(A, B: inbit; Y : outbit);endcomparator;architecturebehavi oral ofcomparator isbeginprocess (A, B)beginif(A = B) thenY <= '1';elseY <= '0';end if;end process;16/37end; entitytb_comparator isendtb_comparator ;architecturesimulation oftb_comparator iscomponentcomparatorcomponentcomparator port(A, B: inbit; Y : outbit);end component;ilil ilbbitsignalsignal_a,signal_b : bit;beginsignal_a <= '0', '1' after20 ns, '0' after40 ns;signal_b <= '0', '1' after10 ns, '0' after20 ns, '1' after30 ns, '0' after40 ns;U0 : comparator port map (A=>signal_a, B=>signal_b, Y=>open);--U0 : comparatorport map(signal a signal b open);U0 : comparator port map (signal_a, signal_b, open);--U0 : comparator port map (Y=>open, A=>signal_a, B=>signal_b);--U0 : comparator port map (open, signal_a, signal_b); -- Not Goodd17/37end.

5 4 bit entitycomparator isport(A, B : inbit_vector(3 downto0); Y : outbit);endcomparator; N bit entitycomparator isgeneric( N : integer); port(A, B : inbit_vector(N-1 downto0); Y : outbit);18/37endcomparator; generic(N : integer := 4); u0: comparatorgeneric map (N => 4)port map(A=>signal a B=>signal b Y=>open); port map (A=>signal_a,B=>signal_b,Y=>open);i(N i t2)generic(N : integer := 2);-- 0ti(N4)u0: comparatorgeneric map (N => 4)port map (A=>signal_a,B=>signal_b,Y=>open);19/37 (d d ) (decoder)A(0)A(1)Y(0)Y(1)A(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)00000000001A(1)A(2)Y(1)Y(2)Y(3)00100 00001001000000100Y(3)Y(4)Y(5)01100001000 10000010000Y(5)Y(6)Y(7)10100100000110010 00000Y(7)1111000000020/37 vhdl vhdl entitydecoder3x8 isport(A : inbit_vector(2 downto0); Y : outbit_vector(7 downto0)); enddecoder3x8;architecturebehavioral ofdecoder3x8 isbeginprocess(A)beginbegincaseA iswhen"000" => Y <= "00000001";h"001" > Y < "00000010"when"001" => Y <= "00000010";-- when"111" => Y <= "10000000";when others=> Y <= "00000001";end case;end process;21/37pendbehavioral.

6 Entitytb_decoder3x8 isendtb decoder3x8 ;endtb_decoder3x8 ;architecturesimulation oftb_decoder3x8 iscomponentdecoder3x8 port(A : inbit_vector(2 downto0); Y : outbit_vector(7 downto0));endcomponent;p;signalsignal_a : bit_vector(2 downto0);beginsignal a <="000""001"after5ns"010"after10 ns"011"after15 nssignal_a <= 000, 001 after5 ns, 010 after10 ns, 011 after15 ns,"100" after20 ns, "101" after25 ns, "110" after30 ns, "111" after35 ns,"000" after40 ns, "001" after45 ns, "010" after50 ns, "011" after55 ns,"100" after60 ns, "101" after65 ns, "110" after70 ns, "111" after75 ns,"000" after80 ns;u0: decoder3x8port map(A=>signal a, Y=>open);22/37u0: decoder3x8 port map (Asignal_a, Yopen);end; 23/37 bl enable enA(2) A(1) A(0) Y(7) Y(6) Y(5) Y(4) Y(3) Y(2) Y(1) Y(0)0 - - - 0000000010000000000110010000001010100000 0100101000000100101100001000110000010000 1100000100001101001000001110010000001110 0100000011111000000024/37 bl vhdl enable vhdl entitydecoder3x8_en isport(A : inbit_vector(2 downto0); EN : inbit;Y : outbit_vector(7 downto0)); enddecoder3x8_en;architecturebehavioral ofdecoder3x8_en isbeginprocess(A EN)process(A, EN)begin25/37 bl vhdl enable vhdl - ifEN = '0' thenY<="00000000";Y < 00000000 ;elsecaseA iswhen"000" => Y <= "00000001";when"000" => Y <= "00000001".

7 When"001" => Y <= "00000010";when"010" => Y <= "00000100";h"011"Y"00001000"when"011" => Y <= "00001000";when"100" => Y <= "00010000";when"101" => Y <= "00100000";when"110" => Y <= "01000000";when"111" => Y <= "10000000";whenothers=> Y <= "00000001";weot e s0000000 ;end case;end if;end process;26/37end process;endbehavioral; bl enable architecturesimulation oftb_decoder3x8_en iscomponentdecoder3x8 encomponentdecoder3x8_en port(A : inbit_vector(2 downto0); EN : inbit;Y : outbit_vector(7 downto0));end component;signalsignal_a : bit_vector(2 downto0);signalen : bit;g;beginen <= '0', '1' after40 ns, '0' after80 ns;signal a <="000""001"after5ns"010"after10 ns"011"after15 nssignal_a <= 000, 001 after5 ns, 010 after10 ns, 011 after15 ns,"100" after20 ns, "101" after25 ns, "110" after30 ns, "111" after35 ns,"000" after40 ns, "001" after45 ns, "010" after50 ns, "011" after55 ns,"100" after60 ns, "101" after65 ns, "110" after70 ns, "111" after75 ns,"000" after80 ns;u0: decoder3x8 enport map(A=>signal a, EN=>en, Y=>open);27/37u0: decoder3x8_en port map (Asignal_a, EN en, Yopen);endsimulation.

8 28/37 (b l hift ) (barrel shifter) (variable length decoding) n : = n x log2(n) 29/37 4 : shift_in (3 downto 0) : mode (1 downto 0) mode (1) : shift mode : 1 rotate shift, 0 logical shift mode (0) : shift direction: 1 left shift, 0 right shift : distance (1 downto 0) 0 3 4 : shift_out (3 downto 0)30/37 shift_in (3 downto 0) = 1101 mode (1 downto 0) = 10 (rotate right shift) distance (1downto0)= 01 distance (1 downto0) 011101 Shift_in1101 Shift_out31/37 shift_in (3 downto 0) = 1101 mode (1 downto 0) = 01 (logical left shift) distance (1downto0)= 10 distance (1 downto0) 101101 Shift_in1000 Shift_out032/37 logical right shift vhdl di ticasedistance iswhen"00" => shift_out(3 downto0) <= shift_in(3 downto0);h"01" > hiftt(3dt0) < '0' & hift i (3dt1)when"01" => shift_out(3 downto0) <= '0' & shift_in(3 downto1);when"10" => shift_out(3 downto0) <= "00" & shift_in(3 downto2).

9 H"11" > hiftt(3dt0) < "000" & hift i (3)when"11" => shift_out(3 downto0) <= "000" & shift_in(3);when others => shift_out(3 downto0) <= shift_in(3 downto0);dend case;33/37 rotate left shift vhdl casedistance iswhen"00" => shift_out(3 downto0) <= shift_in(3 downto0);when"01" => shift out(3downto0) <= shift in(2downto0) & shift in(3);shift_out(3 downto0) <= shift_in(2 downto0) & shift_in(3);when"10" => shift_out(3 downto0) <= shift_in(1 downto0) & shift_in(3 downto2);when"11" => shift_out(3 downto0) <= shift_in(0) & shift_in(3 downto1);when others => shift_out(3 downto0) <= shift_in(3 downto0);end case;34/37 -- mode(1) : shift mode : '1' rotate shift, '0' logical shift-- mode(0) : shift direction : '1' left shift, '0' right shiftifmode(1) = '0' andmode(0) = '0' then -- description of logical shift right modeelsifmode(1) = '0' andmode(0) = '1' then -- description of logical shift left modeelsifmode(1) = '1' andmode(0) = '0' then -- description of rotate shift right modeelse-- mode(1) = '1' andmode(0) = '1'-- description of rotate shift left mode35/37end if; aliasrotate : bit ismode(1);aliasleft : bit ismode(0);();-- ifrotate = '0' andleft