A Glossary of Analog-to-Digital Specifications and ...

1 Sampling SAR ADCO versamplingDelta-Sigma ADCS inglesample perconversionMultiple samples,averagedSignal Noise1 23 4 DataOutPipeline ADC1 23 4 DataOut1 23 4 DataOut1212 ApplicationReportSBAA147B August2006 RevisedOctober2011A 'Delta-Sigma( ),successiveapproximationregister(SAR),a ndpipelineanalog-to- digital (A/D) considerableamountofdetailinthisdocument ,theproductdatasheetfora specificdataconverterproductdatasheet, :RefertoFigure1 whencomparingSAR, pipeline , A/DConvertersSamplingAlgorithmsCompariso n Acquisitiontime,Delta-SigmaA/DConverters TheDelta-Sigma( ) theformofa FiniteImpulseResponse(FIR)orInfiniteImpu lseResponse(IIR) ,theacquisitiontimeis longerthanit is witha SARorpipelineconverter, illustratesoneofthedifferencesbetweenthe samplingmechanismofa SAR,a Pipelineanda theI2C is a a trademarkofMotorola, August2006 RevisedOctober2011A GlossaryofAnalog-to-DigitalSpecification sandPerformanceCharacteristicsSubmitDocu mentationFeedbackCopyright 2006 2011,TexasInstrumentsIncorporatedHoldSam pleHoldAcquisition timeor sample timeAperture timeSample Error(offset, nonlinearity)

2 Input signal123456789 10 11 12 13 14D9D10D8D7D6D5D4D3D2D1D0D11 CSCLKDOUTNull BitAll data transitions occuron the falling edge of SLKS amplePeriodConversion Period15 Clock #15 isoptional;D0 is clocked outon falling edge ofClock # step-inputtothedelta-sigmaconverterinput orswitchesa multiplexeroutputchannel, asnap-shotofthesignalora definedacquisitionpointin timeis required,it is moreappropriatetousea SARA/Dconverter. Acquisitiontime,PipelineA/DConverters Witha pipelineA/Dconverter,theuserinitiatesthe conversionprocesswiththerisingedge(orfal lingedge,asspecifiedin theproductdatasheet) (SampleTime)andApertureTime Acquisitiontime,SARA/DConverters TheacquisitiontimefortheSARconverteris responsetoa (chipselect)drops(witha serialperipheralinterface,orSPI ).

3 Figure3 showsanexampleofa (CS) SARA/DConverterAnalogInput,AnalogBandwid th:Theinputfrequencywherethereconstructe doutputoftheA/Dconverteris ,Capacitance,Common-mode:Thecommon-modec apacitanceofanA/Dconverteris thecapacitancebetweeneachanalogsignalinp ut(s) ,Capacitance,Differential:Thecapacitance betweenthepositiveinput(AIN+) andnegativeinput(AIN ) ofanA/Dconverterwitha GlossaryofAnalog-to-DigitalSpecification sandPerformanceCharacteristicsSBAA147B August2006 RevisedOctober2011 SubmitDocumentationFeedbackCopyright 2006 2011,TexasInstrumentsIncorporated 200mV MaximumDACADCAIN+ ,DifferentialInput:Withtheanalogdifferen tialinput,bothinputpinsoftheA/Dconverter canswingthefullrange,andtypicallychangei n a balancedfashion thatis,asoneinputgoesup,theothergoesdown in a single-supplyconverters, ,witha smallerinputvoltageswingrequiredoneachpi nwhilepreservinga ,Impedance,Common-mode: ,Impedance,Differential:Theimpedancebetw eenthepositiveinput(AIN+) andnegativeinput(AIN ) ofanA/Dconverterwitha ,VoltageRange,Absolute:Theabsoluteanalog voltagerangeofanA/Dconverteris themaximumandminimumvoltagelimitoftheinp utstage(comparedtogroundand/ortheanalogs upplyvoltage).

4 ,thepositiveandnegativepowersuppliesimpo setheselimitsonthedevice,unlessthereis a thereis a resistiveinputnetwork, ,VoltageRange,BipolarInputMode(Different ialInputs):AnA/Dconverterconfiguredina ,neitherinputpingoesbeloworabovetheabsol uteinputvoltagerange.(SeeInputVoltageRan ge DifferentialInputs.)AnalogInput,VoltageR ange,Full-Scale(FSorFSR) Forann-bitconverter, FSis equalto:FS= (2n) (idealcodewidth) Fordelta-sigmaconverters, FSRis oftenusedtoexpressunitsin ,youmayfindINLdefinedat ,theinputrangeoftheA/Dconvertercouldbe ,witha FSR= :AnalogInputs, ,VoltageRange,Pseudo-differential:A pseudo-differentialinputhastwoinputpins, AIN+andAIN , asFigure4 pseudo-differentialinput, (thenegativeinput)canonlyaccepta smallrangeofvoltages,perhapsa fewhundredmillivolts(mV).

5 Thisconfigurationcanbeveryhelpfulin situationswherethesignalhasa ,VoltageRange,Single-ended(unipolarandbi polar):A single-endedinputA/Dconverteris configuredforoneinputvoltagethatis (anddual-supply)partshandlea signalthatmovesbothabovegroundandbelowgr ound,andhavea ,VoltageRange, August2006 RevisedOctober2011A GlossaryofAnalog-to-DigitalSpecification sandPerformanceCharacteristicsSubmitDocu mentationFeedbackCopyright 2006 2011,TexasInstrumentsIncorporatedFull-Sc ale = (AA) (AA)()IN+(MAX)IN (MIN)IN+(MIN)IN (MAX)-----ADCADCI nputININININ+ fs+ fs/2+ fs/2-sf-sf /2-sf /2 VCMVCMVCMVCMS ingle-Ended InputDifferential InputSNR = 20log10( )1(2 f t )pjt =j(ta+ t ) ,VoltageRange,DifferentialInputs.

6 Thedifferentialinputvoltagerangeis equaltothenoninvertinganaloginput(AIN+) minustheinvertinganaloginput(AIN ). Withthesetwoinputpins,theinputvoltageran geis:A positivedigitaloutputis producedwhentheanaloginputdifferentialvo ltage(AIN+ AIN ) is a common-modevoltagebias(VCM)totheinputs,w hichis typicallysettomid-supply(+VS/2).Anextern alsourcecandrivethedifferentialconverter inputsin (ADC,A-DConverter,A/DConverter):AnA/Dcon verteris a devicethatchangesa continuoussignalintoa discrete-time, : Delay Thedelayin timebetweentherisingorfallingedge(typica llythe50%point)oftheexternalsamplecomman dandtheactualtimeatwhichthesignalis Jitter Aperturejitteris ,alongwithclockjitterofthesamplingsystem ,impactstheoverallsignal-to-noiseratio(S NR) equalto:Where: tjis theclockandaperturejitter; f is theclockfrequencyoftheconverterTheapertu reandclockjitteris equalto:Where: tais theroot-mean-squareoftheaperturejitter; tcis theroot-mean-squareoftheclockjitterThere is nocorrelationbetweentheclock-jitterandap erture-jitterterms.

7 Therefore,thesetermscanbecombinedona root-sum-squarebasis(rss). Uncertainty :SamplingoftheA/Dconverterthatis notlockedtothefrequenciesorthetimeofothe rfrequenciesorsamplesin GlossaryofAnalog-to-DigitalSpecification sandPerformanceCharacteristicsSBAA147B August2006 RevisedOctober2011 SubmitDocumentationFeedbackCopyright 2006 2011, :Ina FastFourierTransform(FFT)representationo fconverterdata,theaveragenoiseflooris a calculatedaverageofallofthebinswithinthe FFTplot, (BTC):WiththeBTCcode,thedigitalzero(0000 ,fora 4-bitsystem)correspondstoBipolarZero(BPZ ), digitalcodeof1000,thenapproachesBPZuntil a digitalvalueof1111(fora4-bitsystem)is reachedatoneLSBvaluebelowBPZ(seeTable1). WiththeBTCcodingscheme,themostsignifican tbit(MSB)canalsobeconsidereda a logic'0'a positivevalueis indicated;whentheMSBis a logic'1'a negativevalueis equalto(0111),andtheanalognegativefull-s calerepresentationis (1000).

8 SeeTable1 (1)(2)MNEMONICDIGITALCODEVTR VCODEVTR+ FS1000 FS1100 1 VLSB1111 + + 1 VLSB0001+ + + + + + + + + +FS0100+ + + + + + + + + +FS0111+ + (1)AlsoknownasTwo's ,FSR= 5V.(2)VTR = lowercodetransitionvoltage;VTR+= uppercodetransitionvoltage;VCODE= (digitalcode)10 VLSB, VTR+= VCODE+(1/2)VLSB; VTR = VCODE (1/2) August2006 RevisedOctober2011A GlossaryofAnalog-to-DigitalSpecification sandPerformanceCharacteristicsSubmitDocu mentationFeedbackCopyright 2006 2011, (BOB):BOBcodingbeginswithdigitalzero(000 0,fora 4-bitsystem) ,thecorrespondinganalogvalueapproachesth epositivefull-scalein 1V,leastsignificantbit(LSB)steps, digitalcodeof1000(seeTable2). Thedigitalcountcontinuestoincreasepropor tionallytotheanaloginputuntilthepositive full-scaleis reachedata fulldigitalcount(1111,fora4-bitsystem)as seenin Table2.

9 WithBOBcoding,theMSBcanbeconsidereda signindicator,whereasa logic'0'indicatesa negativeanalogvalue,anda logic'1'indicatesananalogvaluegreatertha norequaltoBipolarZero(BPZ). (1)(2)MNEMONICDIGITALCODEVTR VCODEVTR+ FS0000 FS0100 1 VLSB0111 + + 1 VLSB1001+ + + + + + + + + +FS1100+ + + + + + + + + +FS1111+ + (1)FSR= 5V.(2)VTR = lowercodetransitionvoltage;VTR+= uppercodetransitionvoltage;VCODE= (digitalcode)10 VLSB, VTR+= VCODE+(1/2)VLSB; VTR = VCODE (1/2) GlossaryofAnalog-to-DigitalSpecification sandPerformanceCharacteristicsSBAA147B August2006 RevisedOctober2011 SubmitDocumentationFeedbackCopyright 2006 2011,TexasInstrumentsIncorporatedt =j(ta+ t )c22 SNR = 20log10( )1(2 f t ) : BackgroundCalibration Backgroundcalibrationsarepre-programmeda ndoccurata backgroundcalibration,theconverteris Self-Calibration Oncommand,a self-calibrationoccursastheconverteris , SystemCalibration Oncommand,a ,theconvertercalibratesoffsetandgain,inc ludingtheexternalinputsignal(s).

10 DutyCycle Thedutycycleofa clocksignalis theratioofthetimetheclocksignalremainsat a logichigh(clockpulsewidth) typicallyexpressedasa perfectsquarewaveora differentialsinewaveis 50%. Jitter ThestandarddeviationofclockingtheA/Dconv ertersamplingedge(canbea risingedgeorfallingedge,dependingonthesp ecificA/Dconverter)variationfrompulse-to -pulsein ,andis equalto:Where: tais theroot-mean-squareoftheaperturejitter; tcis theroot-mean-squareoftheclockjitterThere is nocorrelationbetweentheclock-jitterandap erture-jitterterms;therefore,thesetermsc anbecombinedona root-sum-squarebasis(rss).Inmostcases,th eclockjitteris severaltimeshigherthantheA/Dconverterape rturejitter,makingtheclockjitterthedomin antjitternoisesourcein ,alongwithclockjitterofthesamplingsystem , equalto:Where: tjis theclockandaperturejitter.