A modular approach to a VXI Resource Manager

1 This paper was presented as a poster session at is not a discussion documentA modular approach to a VXI Resource Daresbury Lab.,Warrington, .Physics Institute, University of Heidelberg,GermanyAbstractThe EUROGAM collaboration has decided to use 'D' sizeVXI modules for the detector electronics for the Ge and BGOdetectors. This combined with a requirement for controlinformation to be distributed via Ether-net, necessitated thedesign of a slot0 card for board is modular to accommodate any commercialVME processor and to allow for the specification of the VXItrigger basis of the detector electronics for the EUROGAM collaboration1 is the VMEbus eXtensions for Instrumentationspecification [1] (VXI). This uses the VMEbus [2] as a multicomputer control bus, and adds features to enable it to be amulti-vendor open architecture for defines the hardware and software architecture.

2 Thefeatures that are of particular interest are as follows :-- Distributed low skew ECL star lines for high Analog SUM bus for Bussed ECL, and TTL trigger lines for synchronouscontrol of detector electronics Private inter-module backplane bus for use as ECL inpipelined readout, or inter-module communications,or additional analog sum busses, and inspection Larger module sizes, 'D' size : x , withElectromagnetic compatibility specification, andincreased width of Extra power supplies : +/- 24v, , -2v- Autoconfiguration allowing inter change of moduleswith no jumper module is required to provide the minimum VXI slot0functionality, a Resource Manager , VME arbitrator and systemfunction source. Further the module must interface the trigger1A brief overview and a principle introduction to the newData Acquisition can be found in [IEEE NS-37 no2 page 326][5]and analogue signals to the VXI backplane as required by theEUROGAM definition of the connections through the module tothe VXI backplane were not fully defined at the stage when therequirement for the module was first discussed, however therewas a need for such a module at an early stage of the electronicdevelopment for the collaboration to allow the prototypes tobe controlled and tested in a VXI control communication path throughout the dataacquisition system had been chosen to be Ether-net, so themodule needed to provide an interface.

3 The Processor chosenhad to be capable of running the selected software, in this caseVXWorks, and it would be an advantage to have a local disk,hence SCSI. The cost of developing such a board, fromscratch, and the time delays involved were considered to solution was to adopt a modular design philosophyand, where possible purchase ready made sub moduleVXI BackplaneVXI adaptorP3 Sub-moduleVME processorFront panelFig Module ArchitecturePotential VME moduleThe module is formed by a collection of interconnectedsub-modules mounted in a VXI 'D' size module. Theindividual sub-modules are bolted to the module adaptorThis sub-module extends and buffers the VME bus to a pairof DIN 41612 connectors suitable for a 'B' size commercialprocessor, and includes a VME Slave interface.

4 The Slaveprovides the VXI configuration registers, controls for theMODID lines and software access to other are a number of other connectors on this sub-moduleas follows:-Buffered VME bus .Processor P2 connector rows a & bus P2 connector rows a & c .16 bit data and 16 bit address external buswith controls, from the Slave control logic is implemented using an AlteraMAX5128 Erasable Programmable Logic Device (EPLD)[3].This gives the ability to change the use of the Slaveconfiguration registers with configuration registers that are not currently defined,and some that are reserved, are implemented as RAM givingthe ability of software testing of the Slave on bus external bus is implemented as an asynchronoushandshake.

5 There is a strobe signal from the Slave to theexternal bus, to indicate the address is valid, and anacknowledge signal to indicate data is accepted/available inmuch the same way as the VMEbus is write to the data address @26 will enable data onto theexternal data bus, and cause a strobe to occur. The slave andhence the VMEbus then waits for an acknowledge signal fromthe external bus before completing the VME cycle. A Readwill cause a strobe to occur, the slave will then wait for anacknowledge signal from the external bus before completingthe VME buffering are within the VMEbus a number of signals whichcan be considered as asynchronous. These signals are harder tobuffer than those whose direction of drive can be predictedusing the bus grant, bus busy, and R/W lines.

6 The buffersmust be capable of handling signals coming from both sidesat the same time. So when the first isno longer driven from itssource the second continues to drive the first, but when thesecond is no longer driven from its source, then both lines areno longer driven. The problem is further complicated by theneed to use high current open-collector drivers for the VMEbusside. There are 14 such signals, so any solution must not usetoo many solution was found in using a programmable devicewith high current open collector outputs. The device is aPLX448 [4] from PLX technology. See Fig for acircuit. Four of these circuits could be programmed into onedevice, so a total of 4 are used in the final asynchronous buffer bus P2 rows a & c sub-module is connected between the VME buffersub-module and the VXI P3 sub-module.

7 It is positioned overthe VME buffer sub-module as a daughter board, and connectsto the VXI P3 sub-module using a flexible IDC connection. Itis a means of easily configuring the type of buffering to beused on the LBUSC lines . It is also used to control theTTLTRG and ECLTRG lines. The table lists thebuffering used in the collaborations sub-module connects to the VXI P3 connector, the 16bit data and address connector of the VXI adaptor sub-module,and the VXI P2 buffer sub-module. The sub-module providesbuffers and drivers for the ECLTRG, TTLTRG, Clocks, andanalogue signals from the front panel inputs to the backplaneat the P3 connector and via the ribbon cable to the P2 sub-module. A single signal is buffered to drive all the STARX linesfrom the front panel to the backplane, using low skew STARY lines are monitored and the OR is driven to thefront panel.

8 Hardware is provided to ensure that all drivers of VXIbackplane signals will reset to the correct is a 16 bit ADC for monitoring of DC values fromeither the front panel or one of the P2 buffered analog is used in conjunction with multiplexers on the detectorelectronics modules for remote monitoring. Read out andcontrol of the ADC is via a status/control register on this submodule that is accessed using the Slave external is a development program under way at Heidelbergfor a Fast ADC daughter board to provide logic and analoguemonitoring of detector pulses in a one-shot mode . This willbe a daughter board of the P3 sub-module, and will be read outvia the Slave external bus by the VME processor. The inputsfor this will come from the detector electronics via carries the connectors for the processor externalconnectors and external connections to the other sub-units forbuffering to the VXI backplane.

9 This means there has to be aspecific front panel for each processor chosen. But since thecollaboration only intend to use one type for this function itwas not considered a commercial processor must be capable of providing theminimum VME slot 1 functions, and be VMEbus Masterwith A24/D16, A16/D16, and interrupt handler capability. Itwill in the case of EUROGAM also provide an Ether-netinterface, and using a SCSI bus to interface discs, be a standalone software environment. There must also be a target forVXWorks chosen processor in this case is the on and off the collector TTL are thus 14 signals whichpass to the P3 sub-module Thebackplane drivers are enabled as ablock by a control signal from theP3 sub-module. They have specificEurogam signal names on and off the ended two signals are passed to theP3 sub module and controlled as forthe TTLTRG are are terminated and bufferedon this sub-module with outputscapable of driving 50ohm lines.

10 Theoutputs connect to the front is TTL from the P3 are single ended ECL used foran event is buffered with a 50ohmdriver connected to the front is derived on the P3 P2 module VME slave situated in the VXI adaptor sub-module isaccessed in the short-i/o region of the VME address space. It isan A16/D16 slave with interrupter capability. Since it formsthe configuration registers for the VXI slot0 function it has afixed address is 0 in the logical address space of the VXIconfiguration registers space. This address space is part of theshort i/o and VME addresses are calculated from V * 64 +49152, where V is the logical address. This leads to an addressof @C000 for this address space occupies 64 bytes. The function of someof the words are defined in the VXI specification, others areuser definable.