Advanced FinFET Process Technology

1 National Institute of Advanced Industrial Science and TechnologyAdvanced FinFET Process Technology M. MasaharaNational Institute of AIST1 National Institute of Advanced Industrial Science and Technology1. Introduction2. Advanced FinFET Process Technology3. Summary Merits and Issues of FinFET Vth Tuning Vth VariationContents1. Introduction2. Advanced FinFET Process Technology3. Summary Merits and Issues of FinFET Vth Tuning Vth Variation2 National Institute of Advanced Industrial Science and TechnologyMulti-Gate FinFETsSGDSGD1stFinFET Patent in 1980 from AISTFinFET Proposed by AIST in 1980(named FinFET by UCB in 1999) Ultrathin and undoped channel and self-aligned double gate Extremely high short channel effect (SCE) immunity3 National Institute of Advanced Industrial Science and Technology4 DIBL Benchmark FinFETs show the smallest DIBL (=highest SCE immunity)

2 National Institute of Advanced Industrial Science and Technology5 Issues for Advanced FinFET However, several technological issues still SGDSGDFin FormationVth TuningLow ResistiveSource/DrainStress or BulkCompact Model(110) ChannelCparaVariationI/O, ESDN ational Institute of Advanced Industrial Science and Technology1. Introduction2. Advanced FinFET Process Technology3. Summary Merits and Issues of FinFET Vth Tuning Vth VariationContents6 National Institute of Advanced Industrial Science and (NMOS), -VthDG(PMOS) (V)Gate Workfunction (eV)n+-Si ( )p+-Si ( ) (LSTP) (LOP) FinFETs Vthhas a linear relationship with Gate Workfunction For low Vth, dual metal gate (dual WF)

3 Is neededAIST, IEEE TED 20077 National Institute of Advanced Industrial Science and Voltage, Vg [ V ]Drain Current, Id [ A ] Voltage, Vg [ V ]Drain Current, Id [ A ]Weff = mNMOSPMOS|Vd| = 1 V Almost symmetrical Vth s (normally off) are obtained thanks to the midgap work function of TiN ( eV)n+ poly-Si gateTiN-gateSymmetric VthAsymmetric VthId-Vgfor Poly- and TiN-Gate FinFETNMOSPMOS|Vd| = 1 VWeff =17 mLg= 21 mWeff = mLg= 21 mWeff =17 mNational Institute of Advanced Industrial Science and TechnologyDual Metal Gate IntegrationTiN nMOSTaCN pMOSRef.

4 Et al., ESSDERC2007, of TiN and TaCN gate FinFETsEtching residue Deposition and etching General approach: Metal Inter-diffusion This work :(No metal etching)For PMOS Mo( eV)For NMOS Ta( eV)/Mo stack Ta Inter-diffusion in Mo9 National Institute of Advanced Industrial Science and Technology10-310-210-1100051015Ta ion count [arb. unit]Depth [nm]Ta l a y e rMo layerSiO2 TadiffusionAnnealed(700oC 1 h)As +Ta diffusion in MoBack-side SIMS Ta diffuses in Mo and piles-up at Mo/SiO2interface after annealing Thus WF for NMOS is determined by Ta ( )

5 10 National Institute of Advanced Industrial Science and TechnologySiO2HM etchbackin nMOS regionTa and SiO2HM etchbackin pMOS regionPatterning of Mo and Ta/Mo gatesFeatures of Dual MG FinFETsNo metal residue 11 National Institute of Advanced Industrial Science and TechnologyAIST, IEEE EDL 2008I-V for Mo and Ta/Mo FinFETs For NMOS, low Vthcan be achieved by Ta diffusion in Mo For PMOS, low Vthcan be achieved by Mo Off leakage Negligible PMOSMo(high WF)Ta(low WF)low gate WFby Ta diffusionMo(high WF)NMOS12 National Institute of Advanced Industrial Science and TechnologyFour-Terminal FinFETG1G2 SDG1G2 SDVth control gateDrive gate4T- FinFET = Independent DG FinFETIoffIonVg1 IoffIonVg1log IdVthDGVth(G1)

6 Log Id-Vg2+Vg2 DGseparationSGDSGD13 Vth for FinFET can be controlled flexibly and individuallyby separating the DGNational Institute of Advanced Industrial Science and TechnologyDG Separation GSDCMPG1 SDG2 CMP Stopper Image after CMPFinFET FormationDG Separation by CMPGate1 Gate2 SourceDrainFin Top100nmSide Wall Image after LEBFinFET Formation and LithographyDG Separation by LEBR esistBOXsubFinGateStopperCMP ProcessLocal Etch-back Process14 National Institute of Advanced Industrial Science and TechnologyVth Tuning by Controlling Vg2 [ V ]Vth [ V ]S-Slope [ mV/decade ]& Tsi = , = Tsi = 13-nm, = Tsi = 23-nm, = Tsi = 43-nm, = Vth can be tuned from LSTP to HP flexibly by selecting a proper Vg2 (The Second Gate)National Institute of Advanced Industrial Science and Technology1.

7 Introduction2. Advanced FinFET Process Technology3. Summary Merits and Issues of FinFET Vth Tuning Vth VariationContents16 National Institute of Advanced Industrial Science and TechnologyVthVariation for MG FinFETsGDS(1)(2)(3)(5)(4)(2) Fin Thickness (TSi)(3) Oxide Thickness (Tox)(4) RDF(5) Work Function WFV ( m)(1) Gate Length (Lg)PossibleVthVariation Sources17 FinFET variability sources were systematically analyzed National Institute of Advanced Industrial Science and Technology18 Main Cause of Vth Variation NegligibleDimension Variation sources0510 15 20 25 30 35 Measured VthTFinSo urc eLGSourceToxSource mSource LG=6.

8 7 nm (measured) TFin= nm (measured) Tox= nm (measured) Vth[mV]LG= 100 nmTFin= 40 nm<Vth>= VAIST, IEEE EDL 2010 Main Cause Dimension variation sources are negligible Main cause of the Vthvariation is the Workfunction VariationNational Institute of Advanced Industrial Science and Technology Rough etched side wall causes randomly aligned metal grain and thus higher WF variation If side wall is flat, uniformly aligned metal grain and thus lower WF variation can be expectedWorkfunction VariationSDRIEI dealRandomlyaligned MetalHigher WF variation Uniformlyaligned MetalLowerWF variationSi 1-MetalSiO2 SiSiO2G 2-Metal 1-Metal19 National Institute of Advanced Industrial Science and TechnologyAIST, IEDM 2006051015010002000300040005000 Etching time [ min ]Etching Depth [ nm ]214 TMAH50oC(110)(111)(100)359 nm/min9 nm/min051015010002000300040005000 Etching time [ min ]Etching Depth [ nm ]214 TMAH50oC(110)(111)(100)

9 359 nm/min9 nm/min Extremely low ER of (111) in TMAH Flat (111) side wallEtchant TMAH (Resist Developer)(Tetramethylammonium hydroxide)CH3CH3CH3CH3N+OH-CH3CH3CH3CH3N +OH-fin-maskSi-finTMAHBOXSOINano-Wet Etching Process <110> <111>20 National Institute of Advanced Industrial Science and TechnologySourceDrainSi-fin20 nm GateHfin= 45 nmTSi= 12 nmTox 20 nm, TSi = nm, HSi= 45 nm Nano-Wet-Etched FinFET Undoped channel Tox(CET) = nm by C-V Gate Stack : PVD-TiN/SiO2 AIST, VLSI Symp. 2010 SEM and STEM images of FinFET21 National Institute of Advanced Industrial Science and Technology05101520253035400510152025 Vth [ mV ]1/(WL)1/2 [ mm-1 ]PVD-TiN Gate CET = 2.

10 3 nm AVtwas significantly lowered by flattening the side channelAIST, VLSI Symp. 2010 Measured Vthfor Nano-Wet-Etched FinFET 22 National Institute of Advanced Industrial Science and TechnologyAvt BenchmarkRef. #Device StructureGate Stack FDSOI Poly/SiO2 ST ESSDERC20062 FDSOI TiN/HfO2C. Fenouillet-BerangerST IEDM20073 FDSOI (SOTB)NiSi/ Hitachi VLSI20084 Bulk-planar Poly/SiON Selete VLSI20085 Bulk-planar MG/HK ST IEDM20086 Bulk-planar MG/HK Toshiba IEDM20087 Bulk-planar s-Si/SiON Fujitsu IEDM20098 Bulk-planar HK/MG Toshiba VLSI20099 FinFET Mo/SiO2 AIST VLSI200910 Bulk-planar MG/HK ST IEDM200911 Bulk-planar IEDM200912 Bulk-planar IEDM200913 FDSOI MG/HK IBM IEDM200914 FinFET TiN/HfSiO IMEC ESSDERC200915 FinFET TiN/SiO2 VLSI20100123401234 Bulk-planarFDSOIFinFETAvt = Vt(LW)