AN-1520 A Guide to Board Layout for Best Thermal ...

1 1 SNVA183B September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackagesAll trademarksare the propertyof September2006 RevisedApril2013AN-1520A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackagesABSTRACTThis thermalapplicationreportprovidesguidelin esfor the optimalboardlayoutto achievethe best thermalresistancefor ( JA) is highlydependenton the PCB(PrintedCircuitBoard) packageshavingverylow thermalresistancebetweenjunction-to-case ,suchas exposedpad TSSOP(e-TSSOP),exposedpad QFP(e-QFP),and casestudyof the LM2652in a 28-leade-TSSOP packagedemonstratesthe PCBdesignimpacton JA,and generatesdesignrecommendationsto improvethe variouslayoutsof groundplanesbasedon a 3 x3 size and newPCBsreduced JAfromthe rangeof 40 50 C/Wdownto 25 30 (FEA)modelingwas usedfor sensitivityanalysisto identifythe key PCB(PrintedCircuitBoard) of Figures1 CrossSectionViewof ' Viewof 28L (a) The ImageOf IR Camerafor the TemperatureDistributionNearPackageand (b) the TemperaturePlot Alongthe (a), (b) And (c) for the ThreeTypesof PCBB oardsAnalyzedUsingFEA,and (d) ShowsFEAM eshforthe Effectof the DummyRegionsOutsidethe Dog the Board Ideal With28L the Board 4-LayerJEDEC With28L Airflow(a) and DevicePower(b) on the ThermalResistance Die Size(a)

2 And Die AttachMaterial(b) on the ThermalResistance SolderCoverage(a), Diameterof ThermalVias(b), and ThermalVia Distribution(c) on theThermalResistance Distributionon the ThermalResistance September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackagesList of Tables1 DOEof JAResultsOn DOEof TestBoardsand DifferentPowerand DevicePower2W And ThermalPerformancesOf The September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackages1 IntroductionIt is well knownthat the thermalresistanceof the package,especially,thetaJA or JA, (thermalresistancebetweenjunction-to-amb ient)

3 Is highlydependenton the PCBin whichthe partsare mountedfor effectof the PCBis morecriticalwhenthe packagehas extremelylow thetaJC ( JCorthermalresistancebetweenjunction-to- case)becausethe thermalresistancebetweencaseto PCB,andPCBto ambientair, becomesmoredominantthanthat betweendie to is the mainreasonwhy both JCand JAhavebeentypicallyusedto comparethe thermalperformanceof the packageexcludingthe , JAis still consideredas the mostpopularand importantspecificationin the systemengineerneeds JAvalueswhendesigninghis systembasedon the operatingtemperature,not on the temperatureon the conditionof the test PCBfor JAmeasurementshouldbe similarwith that in the real applicationintermsof size and numberof layersof the goal of this applicationreportis to improve JAmeasurementand thermalperformanceby improvingthe test PCB.

4 And suggestguidelinesfor designingthe PCBfor JAmeasurementof applicationengineerneedsto referto this guidelinefor designingthe evaluationboards,especiallyforhigh powerdevicessincethe PCBwill criticallyaffectthe thermalperformance,includingdevicepowere fficiency,SOA(safeoperatingarea),and a 28-leade-TSSOP(ExposedPad ThinShrinkSmallOutlinePackage)was selectedas a differentPCBsweremanufacturedwith variouslayoutsof groundplanein the size of 9 squareinch and 4-layerconfigurationwith 2oz/1oz/1oz/2ozCu. JAresultsand PCBdesignrecommendationspresentedin this applicationreportcan be appliedto otherpackageswith exposedDAP(die attachpaddle),suchas e-QFP(exposedQuadFlat Pack)and LLP(LeadlessLeadframePackage)with differentpin PCB(PrintedCircuitBoard)DesignThe test boardsare 9 squareinch ( ) with a 4-layerCu configurationof 2oz/1oz/1 Figure1, thermalvias connectthe DAPlandingpatternon the top layer,the first interlayerwhichis also assignedas ground,and the differentthermaltest boardsweredesignedtodemonstratethe thermaleffectsof differentlayoutparametersas summarizedin Table1.

5 The layoutfactorsincludethe size of the top groundareacalled dog bone area,connectionto the DAPlandingpattern,numberof thermalvias on groundplanenearthe package(calleddog bonevia, diameter),and the solderresistcoveringthe top and dog boneareais squareforReal#1board,and Real#2has 2 timeslargerdog boneareathanReal# numberof vias in the DAPlandingpattern(DAPvia, diameter)is idealand modifiedJEDEC Board ,therest of the top and bottomlayerscontainthe cross-hatchedCu lineswith 50%Cu top viewpicturesof the five CrossSectionViewof September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackagesTable1. DOEof TestPCBPCBIDD escriptionIdealMaximizeCu groundareafor all layerReal#1 Dog bonegroundin top Full Cu planesin 1st and 2ndinterlayerReal#22 timesdog boneareathanReal#1on top & bottomReal#3(Real#2+ SR)CoverSolderResiston top and bottom;Restis samewithReal#2 ModifiedJEDEC4 layerNo GNDon top and bottomotherthanDAPlanding;Thermalviaconn ected1st interlayerFigure2.

6 ManufacturedPCB's3 TestMethodologyThermalresistanceis definedas the differencein temperaturebetweentwo closedisothermalsurfacesdividedby the total heatflow caseof JAmeasurement: JA= (Tj Ta) September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackageswhere,Tj is the temperaturemeasuredat the semiconductorjunctionand Ta is the ambienttemperature,whichis measuredin a test environmentand fixedat 20 25 C. Pdissis the powerdissipatedby the two waysto powerthe deviceto generateheat,whichare substratediodepoweringand usedfor this test, in whichthe isolateddiodesare foundby usedfor heatingthe deviceand sensingthe temperatureby measuringtheforwardvoltagedropof the diodedependingon the activepoweringtest is tomeasurethe junctiontemperatureand JAwith the deviceon the advantagethat JAis measuredwhilethe deviceis in operation,but theresultscan be moreeasilyinterruptedby showsthe top viewof the LM2652deviceswith pin ids.

7 Figure4 showsthe diodesfoundthroughcurvetracingor internaldrain-to-sourcebodydiodeof the PGNDand PVIN isusedfor monitoringthe junctiontemperatureby measuringforwardvoltagedrop,whileSW and PVIN pathis usedfor heatingthe devicewith showsthe plot of diodevoltagevs. junctiontemperaturemeasuredfromPGNDand PVIN, Top Viewof 28L TSSOPEXPPADF igure4. September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor ExposedPackagesFigure5. LM2652 DiodeVoltagevs. JAThe measurementresultsof thermalresistance JAare shownin Table2 for high two , JAmeasuredwith the sameLM2652package,but with a 2-layerPCBtest Board (explainedunder) is alsolistedfor comparison.(1)Old PCB:2-layer 1oz/1oz,2 inch squaregroundplaneon backsideof PCB,DAPon the top layerconnectedto the bottomlayerwith JAResultsOn DOEof TestBoardsand DifferentPowerand @ 200 LFPM1W @ 400 # # # (modified) PCB(1) well-knownlargeeffectof the airflowconditionand the moderateeffectof devicepoweron JAas shownin Table2, the effectsof boarddesignfactorsare also the resultsofthe 2W heatingconditionin Table2, the effectsof someboarddesignfactorson the thermalresistance JAare summarizedas follows.

8 Effectof PCB:It is obviousthat a high performancemulti-layerPCBhelpsto reduce example, JAis C/Wand 25 C/Won the 2-layerPCBand the Real#3 Board , Effectof groundplanes:The resultof the modifiedJEDEC boardshowsabout21%higher JAthanthatof the high reasonis that the modifiedJEDEC boarddoesnot havegroundplaneson the top and bottomlayersfor heatsinkingeffects. Effectof coppercoverage:The thermalresistance JAof the boards Ideal and Real#2 , as showninTable2, are copperareaon thetop and bottomlayersdecreasesto about50%for the Board Real#2 fromthe maximumcopperareafor the Board Ideal . Effectof solderresistcovering: JAis C/Wand 25 C/Won the Real#2 and Real#3 boards, September2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAN-1520 A Guideto BoardLayoutfor BestThermalResistancefor solderresistcoveringreduces JAby to betterthermalradiation.

9 Effectof dog boneregion: JAis C/Wand C/Won the Real#1 and Real#2 boards, largerdog boneregionwith morevias on the Real#2 boardsreduces JAby 5%.The effectof the dog boneregiondependson the copperlayersand vias of the the caseofless copperlayersand less numberof vias,the effectof the dog boneregionwill ,the dog boneregioncan significantlyimprovethe thermalperformanceof a low definedas= (Tj Ttop)/PdisswhereTjand Ttopare the junctiontemperatureand the temperatureat the top centerof the package, oftenusedto predictthe junctiontemperatureat theend userenvironmentbasedon the temperatureTtop. The temperatureTtopcan be measuredby athermocouplelocatedat the top centerof the dependenton the PCBwith highereffectiveconductivitywill give a lowervalueof. Also,it is dependenton the devicepowerand powerdistributioncalled ChipPowerMap.

10 Table3 showsthe measuredvaluesofof the LM2652packageon the Real#3 boardunderthe devicepowerat 2W and DevicePower2W packagetopcenter known,the junctiontemperaturecan be easilypredictedbasedon the temperatureat the topcenterof the package,whichcan be measuredby usinga thermocoupleor basedon the imagefromanIR showsthe measurementusingan IR camerafor the samesampleusedin Table3under2W (a)is the IR imageand Figure6(b)showsthe temperatureplot alongthemiddleline throughthe packagetop. The temperatureat the top centerof the packageis about68 C,whichis closeto the C in Table3 the top centertemperature68 C C/W,the junctiontemperatureis evaluatedas C basedon the formulaTj=xPdiss+ Ttop, whichis closeto the measuredvalueof the junctiontemperaturein (a) The ImageOf IR Camerafor the TemperatureDistributionNearPackageand(b)