An Overview of LVDS Technology - Texas Instruments

1 DS36C200,DS90C031,DS90C031B,DS90C032,DS9 0C032B,DS90C402,DS90LT012A,DS90LT012AQ,D S90LV011A,DS90LV011AQ,DS90LV012A,DS90LV0 17A,DS90LV018A,DS90LV019,DS90LV027,DS90L V027A,DS90LV027AQ,DS90LV028A,DS90LV028AQ ,DS90LV031A,DS90LV032A,DS90LV047A,DS90LV 048A,DS90LV049,DS90LV049 QAn Overview of lvds TechnologyLiterature Number: SNLA165An Overview of LVDST echnologyINTRODUCTIONR ecent growth in high-end processors, multi-media, virtualreality and networking has demanded more bandwidth thanever before. But the point-to-point physical layer interfaceshave not been able to deal with moving information at thedata rates required. Some of today s biggest challenges thatremain to be solved include: the ability to transfer data fast,lower power systems than currently available, and economi-cal solutions to overcome the physical layer bottleneck. DataTransmission standards like RS-422, RS-485, SCSI and oth-ers all have their own limitations most notably in transferringraw data across a media.

2 Not anymore. Low Voltage Differ-ential Signaling ( lvds ) is a high speed (> Mbps), lowpower general purpose interface standard that solves thebottleneck problems while servicing a wide range of applica-tion application note explains the key advantages and ben-efits of lvds Technology . Throughout this application notethe DS90C031 ( lvds 5V quad cmos differential LineDriver) and the DS90C032 ( lvds 5V quad cmos differen -tial line receiver ) will be used to illustrate the key 50 lvds devices are offered currently (1998) from Na-tional, please refer to the lvds device datasheets for com-plete OVERVIEWT here are two industry standards that define lvds . Themore common of the two is the generic electrical layer stan-dard defined by the TIA. This standard is know as ANSI/TIA/EIA-644. The other application specific standard is an IEEE(Institute for Electrical and Electronics Engineering) standardtitled Scalable Coherent Interface (SCI).

3 ANSI/TIA/EIA-644 This standard was developed under the Data TransmissionInterface committee This standard defines driveroutput and receiver input characteristics. Functional specifi-cations and/or Protocols are not within the scope of the TlAstandard. It notes a recommended maximum data rate of655 Mbps and a theoretical maximum of Gbps basedon a loss-less media; however, maximum data rate is appli-cation (desired signal quality), and device specific (transitiontime). It is feasible that lvds based interface will operate inthe 500 Mbps to range in the near future. Minimummedia specifications are also defined within the standard. Italso discusses failsafe operation of the receiver under faultconditions and other configurations issues such asmulti- receiver operation. National Semiconductor held theeditor position for this SCI-LVDSSCI originally referenced a differential ECL interface withinthe SCI (Scalable Coherent Interface) 1596-1992 IEEE stan-dard.

4 But, this only addressed the high data rates requiredand did not address the low power concerns. Thus,SCI- lvds was defined as a subset of SCI, and is specifiedin IEEE standard. SCI- lvds specifies signaling lev-els (electrical specifications) for the high speed/low powerphysical layer interface. It also defines the encoding forpacket switching used in SCI data transfers. Packets areconstructed from 2-byte (doublet) symbols. This is the funda-mental 16-bit symbol size. No media is specified and thedata rate can be in the order of 500 MT/s based on serial orparallel transmission of 1, 4, 8, 16, 32, 64,.. also supports RamLink for super low power datatransmission in a restricted environment. The IEEE was approved in March 1994. National Semicon-ductor held the Chairperson position for this is similar to the TIA version but differs in someelectrical requirements and load conditions.

5 Both standardsfeature similar driver output levels, receiver thresholds anddata rates. The TIA version is the more generic of the twostandards and is intended for multiple VOLTAGE differential SIGNALINGLVDS Technology uses differential data transmission. Thedifferential scheme has a tremendous advantage oversingle-ended schemes as it is less susceptible to commonmode noise. Noise coupled onto the interconnect is seen ascommon mode modulations by the receivers and is receivers respond only to differential Technology is not dependent on a specific power sup-ply, such as +5V. This means there is an easy migration pathto lower supply voltages such as + , + or even lowerwhile still maintaining the same signaling levels and perfor-mance. Technologies like ECL or PECL are more dependenton the supply voltage. This feature is highly desirable in anyapplication that foresees moving to lower supply voltageswithout substantial redesign or worrying about mixed voltageoperation (+5V/+ ) on system achieve high data rate, low power and to reduce EMl ef-fects, signaling levels have to be reduced.

6 The DS90C031/DS90C032 chipset s limitation on data rate is mainly depen-dent on the Technology driving the lvds drivers. Theaggregate bandwidth that lvds Technology can drive is inthe Gbps range with a loss-less media. Data rates in the500-1,000 Mbps are possible and this limitation is primarilydependent on the media being LEVELSAs the name implies, lvds features alow voltageswingcompared to other industry data transmission signaling levels are illustrated inFigure 1, and a com-parison to PECL levels is also shown as reference. Becauseof the low swing advantage, lvds achieves a high aggre-gate bandwidth in point-to-point applications. National hasrecently introduced a new family of parts called Bus family extends lvds from point-to-point applications tomulti-point applications is fully discussed in other Nationalapplication notes. Bus lvds features similar voltage swings,but provides increased drive current to handle double termi-nations required in multi-point is a registered trademark of National Semiconductor SemiconductorApplication Note 971 Syed B.

7 HuqJohn GoldieJuly 1998An Overview of lvds TechnologyAN-971 1998 National Semiconductor is impossible to achieve high data rates and provide lowpower without utilizing low voltage swings. lvds signalinglevels are smaller (50%) than PECL levels as shown inFig-ure 1. EMI effects are also reduced as the signaling swingsare much smaller than traditional cmos , TTL or even is due to the current mode drivers, the soft transitions,the low switching currents and the use of true differentialdata TERMINATIONLVDS uses a constant current mode driver to obtain its manyfeatures. The value of the current source for the DS90C031is a maximum of mA. The transmission media must beterminated to its characteristic impedance to prevent reflec-tions. Typically this is between 100 120 and is matchedto the actual termination resistor is requiredto gen-erate the differential Output Voltage (VOD) across the resis-tive termination load at the receiver input (seeFigure 2 A).

8 Data transmission from the driver to receiver without the ter-mination is not recommended. The simplicity of the lvds termination scheme makes it easy to implement in most ap-plications. It is recommended to have a single 100 termina-tion between the driver outputs, and the use of surfacemount components is also recommended to reduce the ef-fects of parasitics. The single resistor approach is the mostcommon lvds termination method because of its termination not only avoids reflection problems, butalso reduces unwanted electromagnetic user may also use a cable damping resistor with a ca-pacitor to ground as shown inFigure 2B. This method pro-vides additional common mode termination. Due to the addi-tional complexity, this approach is not too and PECL require more complex terminations than the one resistor solution for lvds . PECL drivers typically re-quire 220 pull down resistors from each driver output toground along with the 100 across the driver outputs asshown inFigure 2C.

9 This termination method requires addi-tional PCB space and increases system cost compared tothe single resistor lvds MODE RANGEAn lvds receiver can tolerate a minimum of 1V groundshift between the driver s ground and the receiver s that lvds has a typical driver offset voltage of + ,and the summation of ground shifting, driver offset voltageand any longitudinally coupled noise is the common modevoltage seen on the receiver input pins with respect to the re-ceiver ground. The common mode range of the receiver is+ to + , and the recommended receiver input voltagerange is from ground to + For example, if a driver has aVOHof and a VOLof (with respect to the driverground), and a +1V ground shift is present (driver ground+1V higher than receiver ground), this will become + ( + ) as VIHand + ( + ) as VILon the receiverinputs referenced to the receiver ground (+ VCM).

10 Simi-larly, with a 1V ground shift and the same driver levels re-sults as ( ) VIHand ( ) VILon the re-ceiver inputs (+ VCM). This is shown graphically inFigure 1. PECL vs lvds Signal FEATUREF ailsafe is a receiver feature that guarantees the output to bein a known logic state (HIGH) under certain fault occurs when the inputs of the receiver are either open,shorted or some applications, not all receivers of the QuadDS90C032 may be used. In this case, the unused receiverinputs should be the receiver does not supportfailsafe and the inputs are leftopen(SeeFigure 4), any ex-ternal noise above the receiver threshold can trigger the out-put and cause an error on the communication line . Since theDS90C032 supports open input failsafe, the receiver outputwill provide an output High for this fault condition can occur if the inputs get acciden-tallyshorted(SeeFigure 4).