Analog Mixed Signal Reference Design Flow - …

1 Analog Mixed Signal Reference Design Flow ( ) July 31, 2013 1/16 CONTENTS 1 Design Flow 3 Detailed AMS Design Flow 4 Library Preparation 2 Analog Mixed Signal Design 5 Block Implementation 6 Why need Analog Mixed Design Flow? TOP Integration 7 Simulation Control 8 Analog Mixed Signal Simulation 9 Layout Chip Assembly 10 Physical Verification 11 Full Chip Level Post Layout Simulation 12 2/16 Why need Analog Mixed Design Flow? Mixed Signal designs have both Analog and digital subsections. The Design environment of Analog and digital are very different. Operation of the system relies on both functionality of each section, and interoperation between the Analog and digital subsections.

2 Design Flow is required to consider Analog and digital together Digital Digital Analog Analog Analog / Digital Approach Analog Mixed Design Approach 3/16 Design Flow Analog Design Flow System level partition Checking for feasibility & testability Spice Simulation Schematic Entry Netlist Verilog - A Physical Design Connectivity Driven Full Custom Physical Verification (DRC / LVS) Design spec. PDK (Symbol) Spice netlist waveform PDK (Pcell) GDSII RC Extraction Post Simulation (Back-annotation) SPF waveform GDS SPF waveform Chip Assembly Placement & Route Sub Sub Sub RC Extraction Full-chip Verification (DRC / LVS) Full-chip Simulation (Back-annotation) Tape-out & Fabrication Tape-out & Fabrication SPEF SPEF DSPF DSPF 4/16 Design Flow Digital Design Flow Synthesis Insert DFT logic - Scan chain - Boundary scan chain - Memory BIST Delay Calc.

3 , STA RTL Pre-layout Simulation ATPG Power Analysis Cell library Gate level netlist(.v) Gate level netlist(.v) Test pattern SDF file (.sdf) Power model (.db) Timing model (.db) waveform Power report Design Spec. P&R RC Extraction IR-drop & EM Analysis Physical Verification (DRC/LVS) Equivalence check Delay Calculation, STA Post-layout Simulation Crosstalk Analysis Tape out & Fabrication Power Analysis Cell library (Milkyway &LEF) DEF SPF SDF Power model Wave form GDS VCD SPF Power report IR-drop report Noise report 5/16 Design Flow Analog Mixed Signal Design Flow Digital Flow (Block) Synthesis Pre logic simulation RTL P&R Physical Verification Analog Flow (Block) Schematic Entry Physical Design Analog specification Physical Verification Mixed Flow (Top)

4 AMS Post Layout Simulation Mixed mode verification AMS simulation Analog Solver Digital simulator Connection model Connection model Gate level netlist DEF, GDS SPF Delay calculation SDF Pre Spice Simulation GDS Tr level netlist Post logic simulation RC Extraction SDF STA/ Delay Calculation RC Extraction Post Spice Simulation SPF Chip Assembly Physical verification 6/16 Design Flow Recommend EDA Tool Version Function EDA Tool Version Schematic Cadence ( virtuoso ) IC or later or later circuit Simulator Cadence (Spectre) or later Synopsys (HSpice) or later Mentor (Eldo) or later Cadence (Ultrasim) or later Synopsys (Hsim) or later Synopsys (NanoSim) or later Synopsys (FineSim-Pro) or later Layout Editor Cadence ( virtuoso ) IC or later or later Synopsys (Laker) 32v4a or later DRC/LVS Checker Mentor (CalibreDRC) or later Cadence (Assura) USR2_HF9 or later Synopsys (Hercules) or later Parasitic Extractor Mentor (CalibreXRC) or later Cadence (Assura QRC) or later Synopsys (Star-RCXT) or later Function EDA Tool Version Synthesis Synopsys( Design Compiler) or later DFT ( Design For Test) Synopsys(DFT-Compiler) or later Synopsys (TetraMAX) or later Mentor (Tessent Memory BIST)

5 Tessent or later Mentor (FastScan) Tessent or later Logic Simulator Cadence(IES) IES or later P&R Cadence(EDI) SOCE 81 USR1 or later Synopsys(ICC) or later Synopsys(Astro) or later Synopsys(Talus Vortex) or later Power Analysis Sequence (PowerTheater) or later Static Timing Analysis Synopsys (PrimeTime) or later Equivalence Check Synopsys (Formality) or later 7/16 Analog Mixed Signal Design Analog Mixed Design Environment Design TEST BENCH Verilog AMS Connection model (setting in ADE) Imported Verilog Gate level netlist DBH DK Symbol View Verilog View (for Digital Simulation) Schematic View (for Analog Simulation) Verilog AMS Connection model (setting in ADE)

6 DBH Analog IP Symbol View SPICE Netlist VerilogA view Analog Block DBH PDK Pcell Symbol view Spectre view Analog PWL Stimulus Verilog Behavioral TESTBENCH Voltage Sources Analog DIGITAL Analog Connection model is used for Converting Digital Signal into Analog Signal and vice versa 8/16 Detailed AMS Design Flow Library Preparation Library/IP STD, IO, Memory, Analog IP and so on Include schematic, layout view in DK Generate verilog view of each cell using verilog model Make veriloga view of Analog IP PDK Include PDK Block implementation Digital Block Generate gate level netlist by Synthesis Analog Block Schematic based implementation Top integration Schematic Entry Digital Block: import verilog netlist and make symbol Analog Block.

7 Make symbol Connect each block in TOP schematic Simulation Control Make test input for AMS simulation Set simulation view each instance in HED Set connection module in ADE Pre layout Simulation Select simulation method in ADE AMS simulation ( Logic Simulator + Spice simulator) Layout Block layout Digital Block: P&R Analog Block: Custom layout TOP layout Import gds file of digital block Connect each block Make iso ring Post layout simulation Parasitic Extraction and Delay Calculation Analog : spef file by LPE Tool Digital: sdf file by Delay Calculation Tool Annotation Spef and sdf file Other procedure is same as Pre layout simulation Physical Verification DRC/LVS Use rule deck in PDK 9/16 PDK Symbol, spectre, hspiceD, auCdl view Library Preparation Make Cadence Library (OA) for each DK and PDK OA DB (Library Manager)

8 Schematic layout symbol verilog veriloga spectre hspiceD auCdl IO cell Schematic, Symbol Verilog view STD cell Schematic, Symbol view Import verilog, Veriloga symbol, verilog, veriloga view Verilog view creation verilog view verilog view STD, IO verilog model IP Verilog, veriloga model IP circuit netlist Make symbol symbol view DBH Data User Data 10/16 Block Implementation Synthesis RTL Gate level netlist Digital Block PDK Import verilog Make Symbol Schematic Design Make Symbol circuit Simulation LIBRARY(OA) Analog Block verilog view schematic view DK Library Preparation Liberty verilog view schematic view Reference Logic Simulation verilog model symbol view Spice model LIBRARY(OA) symbol view spectre view spectre view schematic view Library Preparation Top Integration Top Integration virtuoso virtuoso 11/16 TOP Integration OA (Library Manager) NET LIST Verilog AMS Spectre netlist HSPICE netlist Simulation Control ADE HED Simulator Spectre Ultrasim NC sim Block1 Gate level netlist Block3 schematic IP(MEM) Verilog behavioral model Block3 schematic IP( Analog )

9 Veriloga Block2 RTL Analog Block Digital Block Verilog behavioral TESTBENCH TOP Integration virtuoso AMS simulation Analog stimuls Voltage source Test Bench AMS Design Environment 12/16 Simulation Control Hierarchy Editor (HED) Analog Design Environment (ADE) TOP Digital TOP Analog TOP IO block Logic STD cells Memory Analog block Analog IP IOs nmos pmos verilog verilog verilog verilog verilog verilog schematic schematic veriloga sepectre sepectre schematic Connection Module Setting Simulator Selecting (spectre, Ultrasim, ams) Simulator Option Control Spice Model Including View Binding (verilog,schematic,spectre,veriloga) 13/16 Analog Mixed Signal Simulation Setup 1 2 3 4 Analysis Outputs Simulation AMS Simulator Model Libraries Connect Rules Analysis method Output node Spice or fast spice Netlist and Run Options Netlist and Run The Procedure of AMS Simulation Waveform 14/16 Layout Chip Assembly LOGIC Analog Mux DAC ROSC ADC ADC DAC LOGIC ROSC Analog Mux Custom layout P&R Stream in Extract gds file 15/16 Physical Verification Rules Inputs Outputs GDS DRC report Design Rule Check Review Report file DRC rule deck Setting to run Outputs Run DRC Rules Inputs Outputs GDS LVS report Layout Vs.

10 Schematic Review Report file LVS rule deck Setting to run Outputs Run LVS CDL 16/16 Full Chip Level Post Layout Simulation Post layout simulation Other procedures are same as Pre layout simulation except annotation of SPF and SDF file. Analog block: SPF annotation Digital block: SDF annotation P&R RC Extraction Delay Calculation, STA DEF SPEF SDF SDF generation Physical Design Connectivity Driven Full Custom Physical Verification (LVS) cdl GDSII RC Extraction SPF svdb Schematic Entry SPF generation ADE AMS Simulation Procedure SPF and SDF files are annotated through ADE during AMS simulation