Analysis and design of amplifiers and comparators …

1 Analysis and design of amplifiers and comparatorsin cmos technologyFernando Paix~ao Cortes*, Eric Fabris, Sergio BampiInformatics Institute, Federal University of Rio Grande do Sul (UFRGS), Caixa Postal , Zip , Porto Alegre/RS, BrazilReceived 7 May 2003; received in revised form 23 September 2003 AbstractDesign techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while cmos analogcircuit design is related mostly with the individual experience and background of the designer. Therefore, the design ofan analog circuit depends on several factors such as a reliable design methodology, good modeling and technologycharacterization. Most of this work focuses on the Analysis of several analog circuits, including their functionality, usingdifferent design methodologies.

2 Initially the determination of two key design parameters (slope factornand earlyvoltage VA) and thegm=IDcharacteristics were derived from simulations. Then, the Analysis and design of three diferentanalog circuits are presented. A comparison is made between two design methodology applied to an analog amplifierdesign. The first one is a conventional approach where transistors are in saturation. The second one is based on thegm=IDcharacteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. Theanalog modules for comparison and continuous filtering, that find vast applications today, are then analyzed anddesigned with the parameters and methodology proposed. 2003 Elsevier Ltd. All rights IntroductionThe development of very large scale integration(VLSI) technology, coupled with the demand for moresignal processing integrated in a single chip, has resultedin a tremendous potential for design of analog VLSI systems require analog sub-systems such asamplifiers, comparators , filters, digital- analog and ana-log-digital converters, and so objective of analog circuit design is to map signalconditioning constrains into electronic circuit blocksthat meet those specifications.

3 This task is a challengingactivity because the analog design procedure is based onseveral variables like noise, offset voltages, gain, drifts,etc., that are closely related to transistor sizing (tech-nology dependency). So, the design process imposes todesigners to make some choices based on their experi-ence to achieve a successful work focuses on the Analysis and design ofseveral analog basic circuit blocks. Initially the charac-terization of two key design parameters (the slope factorand early voltage) is addressed. Then, a design meth-odology based on thegm=IDcurve is used for the anal-ysis and design of three different analog circuits: Milleramplifier, track-and-latch comparator and analog approach allows a unified synthesis methodology inall regions of operation of the transistor ranging fromstrong inversion to weak paper is organized as follows: Section 2 discussesthe analog circuit design .

4 Section 3 presents a brief re-view of analog circuit modeling, the characterization oftwo key design parameters is also presented. In Section4, the design methodology based on thegm=IDcurve andits main features are presented, where a quick compar-ison with a conventional design methodology of a Milleramplifier design is demonstrated. The application ofthe methodology to the design of analog modules for*Corresponding (E. Fabris), (S. Bampi).0026-2714/$ - see front matter 2003 Elsevier Ltd. All rights Reliability 44 (2004) 657 and continuous filtering are then presentedin Section 5. Finally, Section 6 presents our analog circuit designThe objective of analog circuit design is to transformspecifications into circuits that satisfy those specifica-tions (schematics, netlists and layout).

5 The designermust understand the process deeply enough to be able tomodel, layout, and test his chips, considering factorssuch as a reliable design methodology, good modelingand technology 1 illustrates the steps of the design process ofCMOS analog integrated circuits based on [1]. The de-signer is responsible for all these steps except , an extensive characterization of the technologymust be developed, where all the parameters that de-scribe the electrical properties of the device are this task is complete, an extensive Analysis andmodeling is made, transforming specifications into cir-cuits with the transistor dimensions calculated. Thisleads to another important task using electrical simu-lation to predict the performance of the circuit . Once theperformance goals are satisfied, the designer is facedwith the task of geometrical description (layout) of thecircuit.

6 Once the layout is finished, it is necessary toinclude the geometrical effects in a post-extraction sim-ulation. If the results are satisfactory, the circuit is readyfor fabrication. In case the specifications are not met,new design iteration must be analog circuit modeling and device characterizationIn order to develop a reliable design methodology forCMOS analog circuit design , an extensive study must bemade aiming good device modeling and accurate tech-nology first step is to characterize the technology aboutto be used in order to extract design parameters neededto the design . Several technology parameters that aresupplied by the foundry are determined from theMOSFET BSIM3v3 model for the AMS tech-nology (Table 1).Based on a conventional design methodology devel-oped in [1,2], a zero-order model for the currentIDandthe output resistancerocan be obtained, consideringthat the transistors are in saturation:ID l0 Cox2 n WL VGS Vt 2 1 where 0<VGS Vt<VDS,ro VAID 2 This simple model is suitable to hand calculations orcomputer Analysis .

7 The primary application of themodel is to simulate or solve the behavior of the behavior includes the biasing of the active devices,including capacitances, and small-signal Analysis (ACanalysis). Observing equations (1) and (2), it becomesclear the necessity of the characterization of two keydesign parameters:n(slope factor), in order to calculatethe bias current, and VA (early voltage), in order tocalculate the output impedance of the Slope factor (n) parameter extractionIn order to calculate the bias current by means of asimple equation (Eq. (1)), the parametern(slope factor)must be considered. The slopencan be translated as theinclination of the log ID versusVGScurve in weakinversion [3].Fig. 1. Steps of the design process of cmos analog integratedcircuits [1].

8 Table 1 Main parameters of the AMS + +17 1 cm2/V ) )07 ) ) )10 ) )10 Cortes et al. / Microelectronics Reliability 44 (2004) 657 664 The extraction method based on [4], consider that theslopencan be obtained as the inverse of the derivative ofVPandVGB. The pinch-off voltage (VP) is defined as thechannel voltage in the edge between the weak and stronginversion [5]. The relation ofIDwithVP VSBcan beobtained through electrical simulation (using theBSIM3v3 model) as shown in Fig. 2. The Is point(normalized current) is chosen to find theVPcorre-spondent. The relation ofVPwithVGBcan be as shown inFig. 3. The value ofncan be obtained as the inverse ofthe derivative ofVPandVGB. The obtained values arenNMOS 1:22 andnPMOS 1 Early voltage (VA) parameter extractionThe output resistance (Eq.

9 (2)) depends directly ofthe parameter VA, the early voltage. This parameter isthe voltage per unit-channel length in analogy with theearly voltage of a bipolar transistor [1]. This parameterdepends directly on the channel lengthLof the extraction method based on [1,2], considers thechannel-length modulation effect variation. Table 2shows the values of VA, obtained through electricalsimulation (using the BSIM3v3 model), as function ofthe transistor lengthLfor a fixed , sometimes the designer must choose theregion of operation of the transistor, and then theW=Lof the transistor can be determined. Therefore, it isinteresting to the designer to obtain the early voltage asfunction of thegm=IDcharacteristic, that gives an indi-cation of the device operation region (see Section 4).

10 Illustrates that. The VA versusgm=IDcurve can beexploited during the design phase, when the transistorslengths are The GM/ID design methodologyMost methods for analytical synthesis of analog cir-cuits suppose that the MOS transistors are either inFig. of a NMOS of a NMOS 4. Thegm=IDversus VA curve NMOS 2VA as function of the transistor length -VGB 3VL(lm)VA (V) Cortes et al. / Microelectronics Reliability 44 (2004) 657 664659strong inversion or in weak inversion. The designmethodology basedgm=IDcharacteristic, proposed by[6], allows a unified synthesis methodology in all regionsof operation the MOS this method, we consider the relationship betweenthe ratio of the transconductancegmover DC draincurrentIDand the normalized drain currentID= W=L as a fundamental design relation to explore the designspace.