AR8316 Data Sheet - jhongtech.com

1 data Sheet December 2009. AR8236 Six-Port Fast Ethernet Switch General Description The AR8236 is a highly integrated Six-port wireless AP router, home gateway, and Fast Ethernet switch with non-blocking xDSL/PON/cable modem platform. The switch fabric, a high-performance lookup Fast Ethernet in the AR8236 complies fully unit with 1024 MAC address, 16 VLAN with IEEE standards. The AR8236. table, and a four-traffic class Quality of implements power saving techniques to Service (QoS) engine. The AR8236 has the facilitate low power consumption. The flexibility to support various networking AR8236 is designed to work in all applications. The AR8236 support many environments. True Plug-n-Play is offload functions to increase the system supported with Auto-Crossover, Auto performance. The AR8236 is designed for Polarity, and Auto-Negotiation in PHYs. Y. cost sensitive switch applications in AR8236 Features Single-chip six-port Fast Ethernet QoS.

2 Switch O P. Support MAC and PHY loopback function for diagnosis Single-chip six-port Fast Ethernet QoS. switch controller with: 5 port 10/100 UTP + 1 port MII MAC. T C .. Fully compliant with IEEE auto-negotiation function Flow control fully supported IEEE flow control for full duplex and back O. 4 port 10/100 UTP + 2 port RMII MAC. pressure for half duplex 4 port 10/100 UTP + 1 port RMII MAC + 1 Supports port lock function N. RMII PHY Supports hardware looping detection QoS support with four traffic classes based Power saving on no link and low traffic rate O. on arrival port, , IPv4 TOS, IPv6 for 10 Base-T. TC and Destination MAC Address Supports Jumbo Frames D. Supports strict priority, WRR, and mix mode (1 SP + 3 WRR or 2 SP + 2 WRR). Full IEEE VLAN ID processing per port and VLAN tagging for 16 VLAN IDs;. and port based VLANs supported Support VLAN tag insert or remove function on per-port basis Support QinQ double tag IGMPv1/v2/v3 and MLDv1/v2 Snooping with hardware join and fast leave function Port states & BPDU handling support Spanning Tree Protocol High performance lookup engine with 1024.

3 MAC Address with automatic learning and aging and support for static addresses Support 40 MIB counters per port Autocast MIB counters to cpu port Support ingress & egress rate limit Broadcast storm Suppression Supports port mirror 2009 by Atheros Communications, Inc. All rights reserved. Atheros , Atheros Driven , Atheros XR , Driving the Wireless Future , ROCm , Super A/G , Super G , Super N , Total , XSPAN , Wireless Future. Unleashed Now. , and Wake on Wireless are registered by Atheros Communications, Inc. Atheros SST , Signal- Sustain Technology , the Air is Cleaner at 5-GHz , and 5-UP are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice. COMPANY CONFIDENTIAL 1. datasheet . AR8236 System Block Diagram Configuration MB/ Statistics LED.

4 Registers Counters Controller MDC / MDIO. EEPROM. 6 Port Fast Ethernet Switch Engine QoS Engine Buffer Memory Queue Manager LED. VLAN Table MDC/. Lookup Engine MAC Table Memory Bandwidth Control MDIO. Port 0 Port 1 Port 2 Port 3 Port 4 Port 5. MAC MAC MAC MAC MAC MAC. 10/ 100 10/ 100 10/ 100 10/ 100 10/ 100. MII Based- T Based- T Based- T Based- T Based- T. PHY PHY PHY PHY PHY. P Y. CO. O T. N. DO. 2 AR8236 Six-Port Fast Ethernet Switch Atheros Communications, Inc. 2 December 2009 COMPANY CONFIDENTIAL. datasheet . General Description .. 1 Mask Control Register .. 31. AR8236 Features .. 1 PORT0 PAD MODE CTRL Register .. 32. AR8236 System Block Diagram .. 2 PORT5 PAD MODE CTRL Register .. 33. Power-on Strapping Register .. 34. 1 Pin Descriptions .. 5 Global Interrupt Register .. 35. Global Interrupt Mask Register .. 36. 2 Functional Description .. 13 Global MAC Address Register . 37. Basic Switch Operation.

5 13 Loop Check Result .. 38. Lookup Engine .. 13 Flood Mask Register .. 38. Automatic Address Learning .. 13 Global Control Register .. 40. Automatic Address Aging .. 14 Flow Control Register 0 .. 42. Media Access Controllers (MAC) .. 14 Flow Control Register 1 .. 42. Port Status Configuration .. 14 QM Control Register .. 43. Full-Duplex Flow Control .. 14 VLAN Table Function Register 0 .. 45. Half-Duplex Flow Control .. 14 VLAN Table Function Register 1 .. 46. Inter-Packet Gap (IPG) .. 14 Address Table Function Register 0 .. 46. Illegal Frames .. 14. Register Access .. 15. LED Control .. 15. PY. Address Table Function Register 1 .. 48. Address Table Function Register 2 .. 48. Address Table Control Register .. 50. EEPROM Description .. 16. VLANs .. 17. Port-Based VLAN .. 17 O. IP Priority Mapping Register 2 .. 51. C. Tag Priority Mapping Register .. 54. Service Tag Register .. 54. VLANs.

6 17. Leaky VLAN .. 17. O. Egress Mode .. 17 T. CPU Port Register .. 55. MIB Function Register 0 .. 55. N. MDIO Control Register .. 56. VLAN Table .. 18 LED Control Register .. 57. IEEE Port Security .. 18 Port Control Registers Summary for all Ports D O. Port Locking .. 18.. 19. Class/Quality of Service .. 19. Priority Scheduling .. 20. Rate Limiting .. 20. 58. Port Status Register .. 60. Port Control Register .. 61. Port-based VLAN Register .. 64. Port-based VLAN Register2 .. 65. Mirroring .. 20 Rate Limit Register .. 67. Broadcast/Multicast/unknown Unicast Storm Priority Control Register .. 67. Control 20 Storm Control Register .. 68. IGMP/MLD Snooping .. 20 Queue Control Register .. 69. Spanning Tree .. 20 Rate Limit Register 1 .. 71. MIB/Statistics Counters .. 21 Rate Limit Register 3 .. 71. Atheros Header Configuration .. 22 Round-Robin Register .. 72. IEEE Reserved Group Addresses Filtering Control 24 4 PHY Control Registers.

7 73. Forwarding Unknown .. 24 Control Register .. 74. Memory Map .. 24 Status Register .. 76. PHY Identifier .. 78. 3 Register Descriptions .. 27 PHY Identifier 2 .. 79. Global Control Registers 0x0000 0x00FC .. 27. Auto-negotiation Advertisement Register .. 80. Port Control Registers 0x0100 0x0124 .. 29. Atheros Communications, Inc. AR8236 Six-Port Fast Ethernet Switch 3. COMPANY CONFIDENTIAL December 2009 3. datasheet . Link Partner Ability Register .. 84. Auto-negotiation Expansion Register .. 86. Function Control Register .. 87. PHY Specific Status Register .. 89. Interrupt Enable Register .. 91. Interrupt Status Register .. 93. Receive Error Counter Register .. 95. Virtual Cable Tester Control Register .. 96. Virtual Cable Tester Status Register .. 97. Debug Port (Address Offset) .. 98. Debug Port 2 (R/W Port) .. 99. Debug Register Analog Test Control .. 100. Debug Register System Mode Control.

8 101. 5 Electrical Characteristics .. 103. Absolute Maximum Ratings .. 103. Y. Recommended Operating Conditions .. 103. P. MII Characteristics .. 103. Power-on Strapping .. 104. Power-on-Reset Timing .. 104. AC Timing .. 105. OSC Timing .. 105. C O. MII Timing .. 106. O. RMII Timing .. 107. SPI Timing .. 108 T. N. MDIO Timing .. 109. Typical Power Consumption Parameters .. 110. D O. 6 Package Dimensions .. 111. 7 Ordering Information .. 115. 4 AR8236 Six-Port Fast Ethernet Switch Atheros Communications, Inc. 4 December 2009 COMPANY CONFIDENTIAL. datasheet . 1. Pin Descriptions This section contains a listing of the pin The following nomenclature is used for signal descriptions (see Table 1-1 on page 7 and types described in Table 1-1 on page 7: Figure 1-1 on page 6). The following nomenclature is used for signal D Open drain for digital pads names: I Digital input signal _L At the end of the signal name, I/O Digital bidirectional signal indicates active low signals IA Analog input signal N_ Near the end of the signal name, indicates active low signals IH Digital input with hysteresis n_.

9 N At the end of the signal name IL Input signals with weak internal indicates the negative side of a pull-down, to prevent signals differential signal from floating when left open Y. NC No connection is made from this O Digital output signal pin to the internal die P. OA Analog output signal P At the end of the signal name, O. indicates the positive side of a P A power or ground signal C. differential signal PD Internal pull-down for digital input O T PU Internal pull-up for digital input N. DO. Atheros Communications, Inc. AR8236 Six-Port Fast Ethernet Switch 5. COMPANY CONFIDENTIAL December 2009 5. datasheet . Figure 1-1shows the package pinout. TXD0/RMII_TXD0_0. TXD1/RMII_TXD1_0. TXEN/RMII_TXEN_0. UART_TXD/MDIO. UART_RXD/MDC. TESTMODE. RESET_L. SPI_CLK. SPI_DO. SPI_CS. SPI_DI. DVDD. AVDD. DVDD. RXN4. RXP4. TXP4. 51. 50. 49. 48. 47. 46. 45. 44. 43. 42. 41. 40. 39. 38. 37. 36. 35. TXCLK/REF_CLK_0 52 34 TXN4.

10 RXD1/RMII_RXD1_0 53 33 AVDD2P5. RXD0/RMII_RXD0_0 54 32 TXN3. XDV/RMII_RXDV_0 55 31 TXP3. Y. 51 35. DVDD_IO 56 34. 30 RXP3. 52. DVDD_IO 57 29 RXN3. P. AR8236 Top View RXD3/RMII_RXD1_1 58 28 AVDD. RXD2/RMII_RXD0_1 27. O. 59 GND RXN2. (Exposed RMII_RXDV_1 60 Ground 26 RXP2. C. RMII_TXEN_1 61 PAD) 25 TXP2. RXCLK/REF_CLK_1 62 24 TXN2. TXD3/RMII_TXD1_1 23. T. 63 AVDD2P5. 68 18. TXD2/RMII_TXD0_1 64 Pin 1 Pin 17 22 TXN1. O. LED_4 65 21 TXP1. LED_3 66 20 RXP1. N. LED_2 67 19 RXN1. LED_1 68 18 AVDD. DO. 10. 11. 12. 13. 14. 15. 16. 17. 1. 2. 3. 4. 5. 6. 7. 8. 9. XTLI. DVDD. DVDD_IO. VDD2P5_REG. VDD_3P3. VDD2P0_REG. VDD1P2_REG. DVDD. XTLO. AVDDVCO. RXP0. LED_0. AVDD2P5. TXN0. TXP0. RXN0. RBIAS. Figure 1-1. 68 pin QFN Package Pinout 6 AR8236 Six-Port Fast Ethernet Switch Atheros Communications, Inc. 6 December 2009 COMPANY CONFIDENTIAL. datasheet . Table 1-1. Signal to Pin Relationships and Descriptions Symbol Pin Type Description Media Connection TXP0 15 IA, OA Media-dependent interface, MDI[4:0]: Transmitter output positive/negative.