ARTIX7 FPGA 修炼秘籍 基于 MIA701 开发板

1 06/28/2017 ARTIX7 FPGA MIA701 FPGA 14 ARTIX7 QQ 543731097 / ARTIX7 / ARTIX7 2017-08-11 / ARTIX7 1 CZ123/ MIA701 VIVADO 4drs -- / ARTIX7 2 ARTIX7 FPGA.

2 1 .. 2 MIA701 FPGA 14 .. 7 S01_CH01_ .. 8 MIA701 .. 8 LED .. 8 DDR LED-D1 .. 9 HDMI .. 9 .. 10 USB .. 11 .. 12 .. 14 .. 16 .. 16 Windriver .. 17 .. 24 PCIE .. 31 S01_CH02 VIVADO .. 36 VIVADO .. 36 VIVADO ( vivado ) .. 36 VIVADO .. 40 .. 41 S01_CH03_USB .. 42 .. 42 runled bit .. 43 .. 44 ( ) .. 45 / ARTIX7 3 S01_CH04_FPGA Verilog .. 46 Verilog HDL .. 46 .. 49 Verilog .. 52 .. 53 Verilog .. 59 .. 59 S01_CH05_FPGA Verilog.

3 64 .. 64 .. 65 .. 66 .. 68 S01_CH06_FPGA Verilog .. 71 Test bench .. 71 .. 71 .. 73 .. 74 .. 77 .. 79 S01_CH07_FPGA_RunLED VIVADO .. 83 .. 83 .. 83 VIVADO .. 84 .. 86 Verilog FPGA .. 90 .. 92 bit .. 95 .. 96 .. 99 / ARTIX7 4 BIN FLASH .. 99 .. 102 S01_CH08_FPGA_Button .. 103 .. 103 .. 104 .. 105 .. 108 .. 108 Chipscope .. 109 .. 109 .. 109 S01_CH09_FPGA .. 110 .. 110 .. 111 VIVADO FPGA .. 111.

4 112 .. 112 .. 113 .. 117 .. 117 .. 120 .. 124 Synthesis .. 129 .. 129 .. 130 .. 130 Implementation .. 131 .. 131 .. 132 / ARTIX7 5 VIVADO .. 133 IP Catalog IA ip core .. 133 .. 137 .. 138 .. 139 S01_CH10_UART .. 140 .. 140 .. 140 .. 141 .. 149 .. 158 .. 158 .. 159 S01_CH11 HDMI .. 160 .. 160 HDMI .. 160 VIVADO .. 163 .. 166 .. 182 bit .. 185 .. 185 .. 188 S01_CH12 CY7C68013 .. 189 .. 189 .. 189 .. 193 Step1: -> -> CyConsole.

5 198 .. 200 .. 202 / ARTIX7 6 S01_CH13_USB STREAM .. 203 .. 203 .. 204 FPGA .. 205 FPGA .. 208 .. 217 .. 218 S01_CH14 CY7C68013A Slave FIFO .. 219 .. 219 Slave FIFO .. 220 Slave FIFO .. 221 Slave FIFO .. 226 USB .. 226 FPGA .. 271 .. 278 .. 280 .. 293 / ARTIX7 7 MIA701 FPGA 14 14 JTAG FPGA VIVADO HMDI FPGA ZYNQ VIVADO FPGA FPGA ZYNQ FPGA / ARTIX7 8 S01_CH01_ MIA701 LED LED.

6 D5 D6 D7 D8 / ARTIX7 9 DDR LED-D1 DDR DDR LED HDMI K2 ( ) / ARTIX7 10 9600 / ARTIX7 11 USB CY7C68013A USB Slave fifo USB / ARTIX7 12 4 IP / ARTIX7 13 FPGA / ARTIX7 14 PCIE

7 PCIE / ARTIX7 15 / ARTIX7 16 PCIE PCIE-Gen2 PCIE PCI / ARTIX7 17 Windriver windriver vs2010 Vs2010 FPGA PC vs2010 windriver Step1 Windriver 8-2-1 1-1-8-1 Step2 next / ARTIX7 18 Step 3: 8-2-1 8-2-3 license string Activate license Y-6-1-5 / ARTIX7 19 Step4 Windriver INF PCIE Y-6-1-6 XILINX PCIe Gneratate.

8 INF file Y-6-1-6 INF / ARTIX7 20 Step5 1) / ARTIX7 21 2) 3) / ARTIX7 22 4) 5) / ARTIX7 23 6) 7) / ARTIX7 24 8) 7 Step1: PCI / ARTIX7 25 Step2: Step3: / ARTIX7 26 Step4: / ARTIX7 27 Step5: Step6: inf / ARTIX7 28 Step7: Step8: / ARTIX7 29 Step9: Step10: / ARTIX7 30 Step11.

9 MIA701_PCIE / ARTIX7 31 PCIE Step1: windriver Step2: VIRTEX5 1-9-4-1 Step3: 2 10ee 7021 / ARTIX7 32 1-9-4-2 Step4: DMA / ARTIX7 33 1-9-4-3 / ARTIX7 34 Step5: DMA / ARTIX7 35 1-9-4-4 / ARTIX7 36 S01_CH02 VIVADO VIVADO Xilinx ISE Vivado Vivado Xilinx 2012 Vivado Xilinx FPGA Xilinx FPGA Vivado ISE Xilinx Vivado Vivado Design Suite User Guide.

10 Getting Started(UG910) Vivado Xilinx 28nm FPGA 28nm ISE Xilinx 2008 4 Vivado Vivado ISE Xilinx FPGA ISE Vivado Vivado ISE ISE XST Core Generator Vivado Vivado Xilinx FPGA Vivado Xilinx 28nm 7 FPGA ZYNQ Virtex-7 Kintex-7 Artix-7 FPGA FPGA 7 FPGA ISE 7 FPGA Vivado ISE vivado SDK VIVADO ( vivado ) 360 / ARTIX7 37 Step1: Step2 NEXT Step3: , NEXT / ARTIX7 38 Step4: Vivado HL System Edition NEXT( ) Step5: SDK NEXT / ARTIX7 39 Step6: NEXT / ARTIX7 40 Step7: VIVADO Step1: vivado Manage Xilinx license Step2: 1 load license 2 Copy license Step3.