AVR Assembler User Guide - GitLab

1 Development Tools User Guide4-1 Section 4 AVR Assembler User to the Atmel AVR Assembler . This manual describes the usage of the Assem-bler. The Assembler covers the whole range of microcontrollers in the AT90S family. The Assembler translates assembly source code into object code. The generated objectcode can be used as input to a simulator or an emulator such as the Atmel AVR In-Cir-cuit Emulator. The Assembler also generates a PROM able code and an optionalEEPROM file which can be programmed directly into the program memory andEEPROM memory of an AVR Assembler generates fixed code allocations, consequently no linking is Assembler runs under Microsoft windows , Microsoft Windows95 andMicrosoft windows NT. In addition, there is an MS-DOS command line version. TheWindows version of the program contains an on-line help function covering most of instruction set of the AVR family of microcontrollers is only briefly described, refer tothe AVR Data Book (also available on CD-ROM) in order to get more detailed knowl-edge of the instruction set for the different get quickly started, the Quick-Start Tutorial is an easy way to get familiar with theAtmel AVR 1022A-A 01/98 AVR Assembler User Guide4-2 Development Tools User Quick Start TutorialThis tutorial assumes that the AVR Assembler and all program files that come with it areproperly installed on your computer.

2 Please refer to the installation StartedStart the AVR Assembler . By selecting File Open from the menu or by clicking on the toolbar, open the file . This loads the assembly file into the Editorwindow. Read the program header and take a look at the program but do not make anychanges Your First FileOnce you have had a look at the program, select Assemble from the menu. A secondwindow (the Message window) appears, containing a lot of error messages. This win-dow will overlap the editor window, so it is a good idea to clean up your work space onthe screen. Select the Editor window containing the program code, and select Window Tile Horizontal from the menu. It is useful to have the Editor window larger than theMessage window, so move the top of the Message window down a bit, and follow withthe bottom of the Editor window. Your screen should look like this:AVR Assembler User GuideDevelopment Tools User and Correcting ErrorsFrom the looks of the Message window, it seems that you have attempted to assemble aprogram with lots of bugs.

3 To get any further, the errors must be found and to the first error message in the Message window (the one reported to be on line54) and press the left mouse button. Notice that in the Editor window, a red vertical baris displayed all over line 54. The error message says that only registers R0 to R31 canbe assigned variable names. That is true since the AVR has exactly 32 General Pur-pose working registers numbered R0-R31, and tries to assign a name toregister 32. See the figure click on the error message in the Message window and observe that the Editorwindow becomes active while the cursor is positioned at the start of the line containingthe error. Correct the mistake by changing r32 to r19 in the Editor window. Onedown, five to go. Now click on the next error in the list. The message Illegal argument type or count , tellsthat something is wrong with the arguments following the compare ( cp ) that the register named BH is one of the arguments, which happens to be thevariable we just corrected.

4 By clicking along on the remaining errors, it appears that thefirst error generated all the messages. find out whether all errors have been corrected, double click on any error (to activatethe Editor window) or click inside the Editor window before you assemble once more. Ifyou have done it all right up till now, the Message window will tell that you are crownedwith success. AVR Assembler User Guide4-4 Development Tools User source The Assembler works on source files containing instruction mnemonics, labels anddirectives. The instruction mnemonics and the directives often take operands. Code lines should be limited to 120 characters. Every input line can be preceded by a label, which is an alphanumeric string terminatedby a colon. Labels are used as targets for jump and branch instructions and as variablenames in Program memory and input line may take one of the four following forms:1.

5 [label:] directive [operands] [Comment] 2.[label:] instruction [operands] [Comment] line A comment has the following form:; [Text]Items placed in braces are optional. The text between the comment-delimiter (;) and theend of line (EOL) is ignored by the Assembler . Labels, instructions and directives aredescribed in more detail :label: .EQU var1=100 ; Set var1 to 100 (Directive).EQU var2=200 ; Set var2 to 200test: rjmp test ; Infinite loop (Instruction); Pure comment line; Another comment lineNote:There are no restrictions with respect to column placement of labels, directives, comments or Assembler User GuideDevelopment Tools User mnemonicsThe Assembler accepts mnemonic instructions from the instruction set. A summary ofthe instruction set mnemonics and their parameters is given here. For a detaileddescription of the Instruction set, refer to the AVR Data :1.

6 Not available in base-line microcontrollersMnemonicsOperandsDescrip tionOperationFlags#Clock NoteARITHMETIC AND LOGIC INSTRUCTIONSADDRd, RrAdd without CarryRd Rd + RrZ,C,N,V,H1 ADCRd, RrAdd with CarryRd Rd + Rr + CZ,C,N,V,H1 ADIWRd, KAdd Immediate to WordRd+1:Rd Rd+1:Rd + KZ,C,N,V2 SUBRd, RrSubtract without CarryRd Rd - RrZ,C,N,V,H1 SUBIRd, KSubtract ImmediateRd Rd - KZ,C,N,V,H1 SBCRd, RrSubtract with Carry Rd Rd - Rr - CZ,C,N,V,H1 SBCIRd, KSubtract Immediate with CarryRd Rd - K - CZ,C,N,V,H1 SBIWRd, KSubtract Immediate from WordRd+1:Rd Rd+1:Rd - KZ,C,N,V2 ANDRd, RrLogical AND Rd Rd RrZ,N,V1 ANDIRd, KLogical AND with ImmediateRd Rd KZ,N,V1 ORRd, RrLogical OR Rd Rd v RrZ,N,V1 ORIRd, KLogical OR with ImmediateRd Rd v KZ,N,V1 EORRd, RrExclusive OR Rd Rd RrZ,N,V1 COMRdOne's ComplementRd $FF - RdZ,C,N,V1 NEGRdTwo's ComplementRd $00 - RdZ,C,N,V,H1 SBRRd,KSet Bit(s) in RegisterRd Rd v KZ,N,V1 CBRRd,KClear Bit(s) in RegisterRd Rd ($FFh - K)Z,N,V1 INCRdIncrementRd Rd + 1Z,N,V1 DECRdDecrementRd Rd - 1 Z,N,V1 TSTRdTest for Zero or MinusRd Rd Rd Z,N,V1 CLRRdClear RegisterRd Rd RdZ,N,V1 SERRdSet RegisterRd $FFNone1 MULRd,RrMultiply UnsignedR1, R0 Rd RrC2 (1)AVR Assembler User Guide4-6 Development Tools User GuideMnemonicsOperandsDescriptionOperati onFlags#Clock NoteBRANCH INSTRUCTIONSRJMPkRelative JumpPC PC + k + 1 None2 IJMPI ndirect Jump to (Z)

7 PC Z None2 JMPkJumpPC k None3 RCALLkRelative Call Subroutine PC PC + k + 1 None3 ICALLI ndirect Call to (Z)PC ZNone3 CALLkCall Subroutine PC kNone4 RETS ubroutine ReturnPC STACKNone4 RETII nterrupt ReturnPC STACKI4 CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3 CPRd,RrCompareRd - RrZ,C,N,V,H1 CPCRd,RrCompare with CarryRd - Rr - CZ,C,N,V,H1 CPIRd,KCompare with ImmediateRd - KZ,C,N,V,H1 SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC PC + 2 or 3 None 1 / 2 / 3 SBRSRr, bSkip if Bit in Register Setif (Rr(b)=1) PC PC + 2 or 3 None 1 / 2 / 3 SBICP, bSkip if Bit in I/O Register Clearedif(I/O(P,b)=0) PC PC + 2 or 3 None1 / 2 / 3 SBISP, bSkip if Bit in I/O Register Setif(I/O(P,b)=1) PC PC + 2 or 3 None1 / 2 / 3 BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC PC+k + 1 None 1 / 2 BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC PC+k + 1 None 1 / 2 BREQ kBranch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2 BRNE kBranch if Not Equalif (Z = 0) then PC PC + k + 1 None 1 / 2 BRCS kBranch if Carry Setif (C = 1) then PC PC + k + 1 None 1 / 2 BRCC kBranch if Carry Clearedif (C = 0) then PC PC + k + 1 None 1 / 2 BRSH kBranch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2 BRLO kBranch if Lowerif (C = 1) then PC PC + k + 1 None 1 / 2 BRMI kBranch if Minusif (N = 1) then PC PC + k + 1 None 1 / 2 BRPL kBranch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2 BRGE kBranch if Greater or Equal, Signedif (N V= 0) then PC PC+ k + 1 None 1 / 2 BRLT kBranch if Less Than, Signedif (N V= 1) then PC PC + k + 1 None 1 / 2 BRHS kBranch if Half Carry Flag Setif (H = 1)

8 Then PC PC + k + 1 None 1 / 2 BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC PC + k + 1 None 1 / 2 BRTS kBranch if T Flag Setif (T = 1) then PC PC + k + 1 None 1 / 2 BRTC kBranch if T Flag Clearedif (T = 0) then PC PC + k + 1 None 1 / 2 BRVS kBranch if Overflow Flag is Setif (V = 1) then PC PC + k + 1 None 1 / 2 BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC PC + k + 1 None 1 / 2 BRIE kBranch if Interrupt Enabledif (I = 1) then PC PC + k + 1 None 1 / 2 BRID kBranch if Interrupt Disabledif (I = 0) then PC PC + k + 1 None 1 / 2 AVR Assembler User GuideDevelopment Tools User Guide4-7 MnemonicsOperandsDescriptionOperationFla gs#Clock NoteDATA TRANSFER INSTRUCTIONSMOVRd, RrCopy RegisterRd RrNone1 LDIRd, KLoad ImmediateRd KNone1 LDSRd, kLoad Direct from SRAMRd (k)None3 LDRd, XLoad IndirectRd (X)None2 LDRd, X+Load Indirect and Post-IncrementRd (X), X X + 1 None2 LDRd, -XLoad Indirect and Pre-DecrementX X - 1, Rd (X)None2 LDRd, YLoad IndirectRd (Y)None2 LDRd, Y+Load Indirect and Post-IncrementRd (Y), Y Y + 1 None2 LDRd, -YLoad Indirect and Pre-DecrementY Y - 1, Rd (Y)None2 LDDRd,Y+qLoad Indirect with DisplacementRd (Y + q)None2 LDRd, ZLoad Indirect Rd (Z)None2 LDRd, Z+Load Indirect and Post-IncrementRd (Z), Z Z+1 None2 LDRd, -ZLoad Indirect and Pre-DecrementZ Z - 1, Rd (Z)None2 LDDRd, Z+qLoad Indirect with DisplacementRd (Z + q)None2 STSk, RrStore Direct to SRAM(k) RrNone3 STX, RrStore Indirect(X) RrNone2 STX+, RrStore Indirect and Post-Increment(X) Rr, X X + 1 None2ST-X, RrStore Indirect and Pre-DecrementX X - 1, (X) RrNone2 STY, RrStore Indirect(Y) RrNone2 STY+, RrStore Indirect and Post-Increment(Y)

9 Rr, Y Y + 1 None2ST-Y, RrStore Indirect and Pre-DecrementY Y - 1, (Y) RrNone2 STDY+q,RrStore Indirect with Displacement(Y + q) RrNone2 STZ, RrStore Indirect(Z) RrNone2 STZ+, RrStore Indirect and Post-Increment(Z) Rr, Z Z + 1 None2ST-Z, RrStore Indirect and Pre-DecrementZ Z - 1, (Z) RrNone2 STDZ+q,RrStore Indirect with Displacement(Z + q) RrNone2 LPMLoad Program MemoryR0 (Z)None3 INRd, PIn PortRd PNone1 OUTP, RrOut PortP RrNone1 PUSHRrPush Register on StackSTACK RrNone2 POPRdPop Register from StackRd STACKNone2 AVR Assembler User Guide4-8 Development Tools User GuideMnemonicsOperandsDescriptionOperati onFlags#Clock NoteBIT AND BIT-TEST INSTRUCTIONSLSLRdLogical Shift LeftRd(n+1) Rd(n),Rd(0) 0,C Rd(7)Z,C,N,V,H1 LSRRdLogical Shift RightRd(n) Rd(n+1),Rd(7) 0,C Rd(0)Z,C,N,V1 ROLRdRotate Left Through CarryRd(0) C,Rd(n+1) Rd(n),C Rd(7)Z,C,N,V,H1 RORRdRotate Right Through CarryRd(7) C,Rd(n) Rd(n+1),C Rd(0)Z,C,N,V1 ASRRdArithmetic Shift RightRd(n) Rd(n+1), n= ,C,N,V1 SWAPRdSwap NibblesRd( ) Rd( )None1 BSETsFlag SetSREG(s) 1 SREG(s)1 BCLRsFlag ClearSREG(s) 0 SREG(s)1 SBIP, bSet Bit in I/O RegisterI/O(P, b) 1 None2 CBIP, bClear Bit in I/O RegisterI/O(P, b) 0 None2 BSTRr, bBit Store from Register to TT Rr(b)T1 BLDRd, bBit load from T to RegisterRd(b)

10 TNone1 SECSet CarryC 1C1 CLCC lear CarryC 0 C1 SENSet Negative FlagN 1N1 CLNC lear Negative FlagN 0 N1 SEZSet Zero FlagZ 1Z1 CLZC lear Zero FlagZ 0 Z1 SEIG lobal Interrupt EnableI 1I1 CLIG lobal Interrupt DisableI 0 I1 SESSet Signed Test FlagS 1S1 CLSC lear Signed Test FlagS 0 S1 SEVSet Two's Complement OverflowV 1V1 CLVC lear Two's Complement OverflowV 0 V1 SETSet T in SREGT 1T1 CLTC lear T in SREGT 0 T1 SEHSet Half Carry Flag in SREGH 1H1 CLHC lear Half Carry Flag in SREGH 0 H1 NOPNo OperationNone1 SLEEPS leepNone1 WDRW atchdog ResetNone1 AVR Assembler User GuideDevelopment Tools User Guide4-9 The Assembler is not case sensitive. The operands have the following forms:Rd:R0-R31 or R16-R31 (depending on instruction)Rr:R0-R31 b:Constant (0-7), can be a constant expressions:Constant (0-7), can be a constant expressionP:Constant (0-31/63), can be a constant expressionK:Constant (0-255), can be a constant expressionk:Constant, value range depending on instruction.