Basics of Electrostatic Discharge Protection

1 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 1 Basics of Electrostatic Discharge (ESD) Protection Prof. Mayank Shrivastava Department of Electronic Systems Engineering Indian Institute of Science Bangalore Outline Capacitance and ESD on Chip (SoC) Standards HBM CDM IC level Protection Protection devices ESD Concepts Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 2 Outline Capacitance and ESD on Chip (SoC) Standards HBM CDM IC level Protection Protection devices ESD Concepts Prof. Mayank Shrivastava, DESE, IISc oHuman body together with its surroundings forms a capacitance absolute value depends on the body mass and surrounding ( humidity and temperature) Q: Is it good or bad?

2 Why? Q: Is there any application/use of body capacitance? oBody capacitance applications: to operate pushbutton switches, in elevators touch screens of smart phones, tablets, etc. capacitive touch sensors in touch screens responds to close approach (but not force of touch) of a human body , usually a fingertip The capacitance between the device itself and the fingertip is sensed because of body capacitance, people act as good antennas a high body capacitance is an indicator of large quantities of intact cellular membranes used in few medical tests oAny disadvantage? Yes, Electrostatic Discharge ! body Capacitance Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof.

3 Mayank Shrivastava, DESE, IISc 3 ++++++++ Electrostatic Discharge (ESD) RDUTCSUBRSUBPAD Discharge Path o Charge can be stored or accumulated across physical bodied (if isolated from ground) o It can be a human body , a machine or the electronic equipment ( IC) itself (In general) ESD is the transfer of Electrostatic charge between bodies (or surfaces) at different Electrostatic potential Electrical Overstress (EOS): Exposure of an object to current or voltage beyond its physical limits (max. ratings). ESD is a subject of EOS. Prof. Mayank Shrivastava, DESE, IISc ESD EOS Specific Lightning - High Voltage (1V 15kV) - Short Duration (< 1ms) - Very Low Power - Low Rise Time (1-10ns) - Low Voltage - Longer Duration (> 1ms) - Low Power - High Rise Time (~ 10ms) - Extremely High Voltage - Extremely High Power EOS In-General ICs used in automotive, military, medical, consumer, etc.

4 Electronics can be damaged with ESD and EOS Houses, Buildings Airplanes, Electronics, etc. ESD Regime EOS Regime Pf (Log) tf (Log) ~ 1 ~ 1/2 ~1log( ) ~ 1 ~ 1/2 ~1log( ) ~1log( ) Constant Power Dwyer, SSE, 1990 (modified) o ESD: Heat does not disperse much localized failures o EOS: Wide spreading of heat large areas of damage Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 4 Grounding Person Wrist Strap to Ground (or flooring/footwear) 1 Grounded Work Surface 2 ESD Protective Packaging 3 ESD for Layman Prof. Mayank Shrivastava, DESE, IISc ESD: Factory Measures System Level ESD IC Level ESD Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof.

5 Mayank Shrivastava, DESE, IISc 5 ESD Q-Test Standards IC level ESD - human body model (HBM): ANSI ESDA/JEDEC JS-001 - Charged device model (CDM): JESD 22-C101C Systems level ESD - IEC 61000 -4-2 - ISO 10605 (automotive) - Cable Discharge events (CDE) (company specific test specs) Prof. Mayank Shrivastava, DESE, IISc Outline Capacitance and ESD on Chip (SoC) Standards HBM CDM IC level Protection Protection devices ESD Concepts Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 6 CPU v/s SoC Products PC Client Data Center CPU Netbook & Tablet Smart Phones Embedded Consumer Electronics Wireless SoC Prof. Mayank Shrivastava, DESE, IISc Progress in SoC Integration 2012 5.

6 PA 2008 4. FM Radio 2006 3. Power Manage-ment Unit 2005 2. RF Trans-ceiver 2000 1. Digital Baseband Analog Baseband Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 7 Outline Capacitance and ESD on Chip (SoC) Standards HBM CDM IC level Protection Protection devices ESD Concepts Prof. Mayank Shrivastava, DESE, IISc ESD: Electrostatic Discharge An event of electrical Discharge from one body to other Discharge Path + + + + + + Pre-charged Chip RPAD CSUB RSUB PAD < Charged Device model CDM RDUT CSUB RSUB PAD + + + + + + + + human body model HBM Discharge Path Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof.

7 Mayank Shrivastava, DESE, IISc 8 (A)Time (ns)Stress (& test) Models HBM: human body model Rise Time = 10ns Peak Current = Av. Stress time = 100ns Target = 2KV RHBM = C CHBM = 100pF L DUT (RL) human body Tester parasitic L: Parasitic inductance C: Test board capacitance RL=0 Prof. Mayank Shrivastava, DESE, IISc 02004006000246810 Current (A)Time (ps)Stress (& test) Rise Time = 100ps Peak Current = 10A Av. Stress time = Target = 500V CDM: Charged Device model Field PlateInsulator50 co-axPogo PinDUTGND PlateHV Supply>100M Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 9 Charged Device model (CDM) Test Setup Prof.

8 Mayank Shrivastava, DESE, IISc ESD Waveforms [Gieser] (modified)1-16A~ Current100-500ps10-15ns2-10nsRise Time~1ns~40ns~150nsPulse Width500V200V2kVQuallevelsCDMMMHBMM odel1-16A~ Current100-500ps10-15ns2-10nsRise Time~1ns~40ns~150nsPulse Width500V200V2kVQuallevelsCDMMMHBMM odel-3036912020406080100120 Time, t (ns) Discharge Current, IESD(A)500V CDM2000V HBM200V MMTypical CDM peak current range15oCDM Discharge leads to very high, short current spikes oESD Protection must limit excess voltage at gate oxides due to high current Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 10 ESD Device characterization: Transmission Line Pulsing Device characterization with rectangular pulses which are generated by a Transmission Line Pulser (TLP) HV 0 - Mega Ohms 50 transmission line ( 5m) DUT Switch [A]voltage [V]I-V data [A]time [ns]averagedcurrent0123456-200204060volt age [V]time [ns]averagedvoltageVoltage probe Current probe Prof.

9 Mayank Shrivastava, DESE, IISc ESD Consequences VDD VSS I/P PAD Internal Circuit VDD VSS O/P PAD - + - + Prof. Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 11 Failure Mechanism Failure: Device Level Failure: System Level Oxide Breakdown (Left: Gate Oxide Right: LOCOS) Thermal Melting (Left: Silicon Right: Metal) oCDM type fails causes breakdown of thin dielectrics oHBM type fails causes thermal fails of silicon device or weak interconnects oSystem level ESD or EOS causes much more extended fails Physical Failure Signature Outline Capacitance and ESD on Chip (SoC) Standards HBM CDM IC level Protection Protection devices ESD Concepts Prof.

10 Mayank Shrivastava, DESE, IISc 20-11-2013 Prof. Mayank Shrivastava, DESE, IISc 12 (Simplified) ESD Protection - VDD VSS I/P PAD Internal Circuit VDD VSS O/P PAD ESD ESD ESD ESD + - + (unwanted) Voltage Drop (unwanted) Current Path Tradeoffs: ESD robustness vs. Circuit level System/IC level Area Yield and cost Leakage Design time/cycle Performance Time to market Complexity and design difficulty Testing and qualification requirements Prof. Mayank Shrivastava, DESE, IISc ESD Design Window oESD design space is governed by: thermal failure limits (second breakdown) reliability constraints (dielectric breakdown) oESD design space is limited by: shrinking technology interconnect resistance and capacitive loading Prof.