CA3130, CA3130A Datasheet - renesas.com

1 Datasheet . ca3130 , CA3130A FN817. 15 MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output Aug 1, 2005. CA3130A and ca3130 are op amps that combine the Features advantage of both CMOS and bipolar transistors. MOSFET Input Stage Provides: Gate-protected P-Channel MOSFET (PMOS) transistors are - Very High ZI = T ( x 1012 ) (Typ). used in the input circuit to provide very-high-input - Very Low II .. 5pA (Typ) at 15V Operation impedance, very-low-input current, and exceptional speed .. = 2pA (Typ) at 5V Operation performance. The use of PMOS transistors in the input stage Ideal for Single-Supply Applications results in common-mode input-voltage capability down to below the negative-supply terminal, an important Common-Mode Input-Voltage Range Includes attribute in single-supply applications.

2 Negative Supply Rail; Input Terminals can be Swung Below Negative Supply Rail A CMOS transistor-pair, capable of swinging the output voltage to within 10mV of either supply-voltage terminal (at CMOS Output Stage Permits Signal Swing to Either (or both) Supply Rails very high values of load impedance), is employed as the output circuit. Pb-Free Plus Anneal Available (RoHS Compliant). The ca3130 Series circuits operate at supply voltages Applications ranging from 5V to 16V, ( to 8V). They can be phase compensated with a single external capacitor, and have Ground-Referenced Single Supply Amplifiers terminals for adjustment of offset voltage for applications Fast Sample-Hold Amplifiers requiring offset-null capability. Terminal provisions are also made to permit strobing of the output stage.

3 Long-Duration Timers/Monostables High-Input-Impedance Comparators The CA3130A offers superior input characteristics over (Ideal Interface with Digital CMOS). those of the ca3130 . High-Input-Impedance Wideband Amplifiers Ordering Information Voltage Followers ( Follower for Single-Supply D/A. PART NO. TEMP. PKG. Converter). (BRAND) RANGE (oC) PACKAGE DWG. #. CA3130AE -55 to 125 8 Ld PDIP Voltage Regulators (Permits Control of Output Voltage CA3130AM -55 to 125 8 Ld SOIC Down to 0V). (3130A). Peak Detectors CA3130AM96 -55 to 125 8 Ld SOIC (3130A) Tape and Reel Single-Supply Full-Wave Precision Rectifiers ca3130 AMZ -55 to 125 8 Ld SOIC (3130AZ) (Note) (Pb-free) Photo-Diode Sensor Amplifiers ca3130 AMZ96 -55 to 125 8 Ld SOIC (3130AZ) (Note) Tape and Reel (Pb-free) Pinout CA3130E -55 to 125 8 Ld PDIP ca3130 , CA3130A .

4 CA3130EZ -55 to 125 8 Ld PDIP* (PDIP, SOIC). (Note) (Pb-free) TOP VIEW. CA3130M -55 to 125 8 Ld SOIC (3130). OFFSET 1 8 STROBE. CA3130M96 -55 to 125 8 Ld SOIC NULL. (3130) Tape and Reel INV. 2 7 V+. INPUT - CA3130MZ -55 to 125 8 Ld SOIC NON-INV. +. (3130MZ) (Note) 3 6 OUTPUT. (Pb-free) INPUT. CA3130MZ96 -55 to 125 8 Ld SOIC V- 4 5 OFFSET. (3130MZ) Tape and Reel (Pb-free) NULL. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets;. molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

5 Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN817 Page 1 of 17. Aug 1, 2005. ca3130 , CA3130A . Absolute Maximum Ratings Thermal Information DC Supply Voltage (Between V+ And V- Terminals) ..16V Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W). Differential Input Voltage ..8V PDIP Package* .. 115 N/A. DC Input Voltage .. (V+ +8V) to (V- ) SOIC Package .. 160 N/A. Input-Terminal Current .. 1mA Maximum Junction Temperature (Plastic Package) ..150oC. Output Short-Circuit Duration (Note 1).. Indefinite Maximum Storage Temperature Range .. -65oC to 150oC. Maximum Lead Temperature (Soldering 10s) ..300oC. Operating Conditions (SOIC - Lead Tips Only).

6 Temperature Range .. -50oC to 125oC *Pb-free PDIPs can be used for through hole wave solder process- ing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified ca3130 CA3130A . TEST. PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS.

7 Input Offset Voltage |VIO| VS = - 8 15 - 2 5 mV. Input Offset Voltage VIO/ T - 10 - - 10 - V/oC. Temperature Drift Input Offset Current |IIO| VS = - 30 - 20 pA. Input Current II VS = - 5 50 - 5 30 pA. Large-Signal Voltage Gain AOL VO = 10VP-P 50 320 - 50 320 - kV/V. RL = 2k . 94 110 - 94 110 - dB. Common-Mode CMRR 70 90 - 80 90 - dB. Rejection Ratio Common-Mode Input VICR 0 to 12 10 0 to 12 10 V. Voltage Range Power-Supply VIO/ VS VS = - 32 320 - 32 150 V/V. Rejection Ratio Maximum Output Voltage VOM+ RL = 2k 12 - 12 - V. VOM- RL = 2k - - V. VOM+ RL = 15 - 15 - V. VOM- RL = - 0 - 0 V. Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA. IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA. Supply Current I+ VO = , - 10 15 - 10 15 mA.

8 RL = . I+ VO = 0V, - 2 3 - 2 3 mA. RL = . FN817 Page 2 of 17. Aug 1, 2005. ca3130 , CA3130A . Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = , TA = 25oC. Unless Otherwise Specified ca3130 , PARAMETER SYMBOL TEST CONDITIONS CA3130A UNITS. Input Offset Voltage Adjustment Range 10k Across Terminals 4 and 5 or 22 mV. 4 and 1. Input Resistance RI T . Input Capacitance CI f = 1 MHz pF. Equivalent Input Noise Voltage eN BW = , RS = 1M 23 V. (Note 3). Open Loop Unity Gain Crossover Frequency CC = 0 15 MHz (For Unity Gain Stability 47pF Required.) fT. CC = 47pF 4 MHz Slew Rate: SR. Open Loop CC = 0 30 V/ s Closed Loop CC = 56pF 10 V/ s Transient Response: CC = 56pF, CL = 25pF, Rise Time tr s RL = 2k.

9 Overshoot OS (Voltage Follower) 10 %. Settling Time (To < , VIN = 4VP-P) tS s NOTE: 3. Although a 1M source is used for this test, the equivalent input noise remains constant for values of RS up to 10M . Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC. Unless Otherwise Specified (Note 4). PARAMETER SYMBOL TEST CONDITIONS ca3130 CA3130A UNITS. Input Offset Voltage VIO 8 2 mV. Input Offset Current IIO pA. Input Current II 2 2 pA. Common-Mode Rejection Ratio CMRR 80 90 dB. Large-Signal Voltage Gain AOL VO = 4VP-P, RL = 5k 100 100 kV/V. 100 100 dB. Common-Mode Input Voltage Range VICR 0 to 0 to V. Supply Current I+ VO = 5V, RL = 300 300 A. VO = , RL = 500 500 A. Power Supply Rejection Ratio VIO/ V+ 200 200 V/V.

10 NOTE: 4. Operation at 5V is not recommended for temperatures below 25oC. FN817 Page 3 of 17. Aug 1, 2005. ca3130 , CA3130A . Schematic Diagram CURRENT SOURCE FOR CURRENT SOURCE 7 V+. BIAS CIRCUIT Q6 AND Q7 LOAD FOR Q11. Q1 Q2 Q3. D1. Z1 D2. Q4 Q5. D3. R1 D4. 40k R. 2. 5k SECOND. STAGE. INPUT STAGE. NON-INV. D5 D6 (NOTE 5) D7 D8. INPUT. 3 OUTPUT. + STAGE Q8. Q6 Q7 OUTPUT. 2. - 6. R3 R4. 1k 1k . Q9 Q10. Q12. Q11. R5 R6. 1k 1k . 5 OFFSET NULL 1 COMPENSATION 8 STROBING 4 V- NOTE: 5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage. Application Information Circuit Description the ohmic load resistance presented to the amplifier is very Figure 1 is a block diagram of the ca3130 Series CMOS high ( ,when the amplifier output is used to drive CMOS.)