Cadence OrCAD 17.2-2016 新功能介紹 - …

1 Cadence OrCAD Date 2016 / 06 / 08 Author Graser SPB Team Revision 1 Version : Cadence OrCAD OrCAD PCB OrCAD capture OrCAD capture CIS OrCAD PSpice OrCAD PCB Editor Cadence Cadence 64 Cadence OrCAD Allegro Cadence OrCAD Allegro /tools/bin PATH pcb/bin fet/bin Cadence OrCAD Allegro PATH Cadence SPB Switch Release (batch file) (batch programs)

2 /tools/bin OrCAD Products TCL 64 OrCAD capture capture Compare Design capture Tools >> Compare Designs Show Details capture OrCAD capture Option >> Preference >> More Preference Extended Preferences Setup (Command Shell) (Design and Libraries) (Design Cache) (DRC) OrCAD capture CIS (CIS) (NetGroup) (NetList) (Schematic) Cadence 150 OrCAD capture OrCAD capture CIS OrCAD capture OrCAD PSpice OrCAD capture File Open Demo Design XML OrCAD capture File Export Design XML Library XML File Import Design XML Library XML < >\tools\ capture \tclscripts\capdb\ XML XML Intel Schematic Export Format (ISCF)

3 OrCAD capture File Export ISCF Intel Schematic Export Format (ISCF) PDF OrCAD capture ghostscript 32 ghostscript 64 Adobe Acrobat File Export PDF PDF OrCAD capture off-page connector OrCAD capture PDF OrCAD capture PDF cross-probing OrCAD PSpice capture PSpice OrCAD capture capture - PSpice OrCAD PSpice Intersheet Reference X OrCAD capture CIS

4 (Crystal Report) OrCAD capture CIS ODBC (Crystal Report) SQLite DRIVER=SQLite3 ODBC Driver;Database= SQLite DB file Name ;LongNames = 0;Timeout = 1000; NoTXN = 0;SyncPragma=NORMAL;StepAPI=0;NoWCHAR=1; OrCAD PSpice PSpice DMI (Device Modeling Interface)Template Code PSpice PSpice (Model Editor) DMI (Device Modeling Interface)Template Code PSpice (Adaptor code) PSpice PSpice PSpice DMI DLL C/C++ SystemC (Model) (Model Code) PSpice Microsoft Visual Studio Express 2013 PSpice DMI DLL Spice DMI DLL PSpice (.)

5 Lib) PSpice OrCAD capture PSpice PSpice PSpice DMI Template Code (Generic device) (Voltage-Controlled Voltage Source) (Function-Dependent Voltage Source) (Voltage-Controlled Current Source) (Function-Dependent Current Source) (Generic Two-Node Device) (Generic Three-Node Device) C/C++ SystemC Verilog-A (Delay) DelayT() DelayT1() TLINE Laplace DelayT() delayt(v(x),<delay time>, <maxdelay>) E2 out 0 value {delayt(V(x),5m, 10m)} DelayT1() delayt1(v(x),<delay time>) E2 out 0 value {delayt1(V(x),5m)}.

6 OPTIONS Flag SKIPTOPO Flag SKIPTOPO = 1 OrCAD capture (topology checks) .options SKIPTOPO = 1 (Hysteresis voltage) (threshold voltage) OrCAD PCB Designer Padstack Padstack Editor Padstack Start Pin/Via Dyn_clearance_oversize_array Dyn_clearance_type Dyn_fixed_therm_width_array Dyn_max_thermal_conns Dyn_min_thermal_conns Dyn_oversize_therm_width_array Dyn_thermal_best_fit Dyn_thermal_con_type Constraint Manager Unused Pad Suppression Embedded Component Solder mask, Paste.

7 Material 250 Cross Section Editor Classes Subclass Class Design_Outline CUTOUTS subclasses Board Geometry Design_Outline CUTOUTS subclass (Inter Layer Checks / ILC) mask Inter Layer Checks Pin, Via Pad Cross section chart Taper trace Taper trace Shape Color Dialog Color dialog Layers / Nets / Display / Favorites / Visibility Pane Filter Visibility pane Status bar

8 Line to Pad Line to Shape Shape Edge to Edge Line to Line Check holes within pads Hole Pad CM Spacing Hole Refresh Symbol Padstacks Replace Padstack Refresh Symbol Padstack CPU 10-20% Import logic Pin Device(>2k pins) Default internal 32 255