Cadence Verilog -A Language Reference

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4 Cadence does not warrant that use of such information will not infringe any third partyrights, nor does Cadence assume any liability for damages or costs of any kind that may result from use ofsuch Rights:Use, duplication, or disclosure by the Government is subject to restrictions as set forthin and et seq. or its Verilog -A Language ReferenceNovember 20043 Product Version .. 19 Related Documents .. 19 Internet Mail Address .. 20 Typographic and Syntax Conventions .. 201 Modeling Concepts.. 23 Verilog -A Language Overview .. 24 Describing a System .. 25 Analog Systems .. 26 Nodes.

5 26 Conservative Systems .. 27 Signal-Flow Systems .. 27 Mixed Conservative and Signal-Flow Systems .. 27 Simulator Flow .. 282 Creating Modules.. 31 Overview .. 32 Declaring Modules .. 32 Declaring the Module Interface .. 33 Module Name .. 34 Ports .. 34 Parameters .. 36 Defining Module Analog Behavior .. 37 Defining Analog Behavior with Control Flow .. 38 Using Integration and Differentiation with Analog Signals .. 39 Using Internal Nodes in Modules .. 40 Using Internal Nodes in Behavioral Definitions .. 40 Using Internal Nodes in Higher Order Systems.

6 41 ContentsCadence Verilog -A Language ReferenceNovember 20044 Product Version Modules with Netlists .. 423 Lexical Conventions .. 43 White Space ..44 Comments ..44 Identifiers .. 44 Ordinary Identifiers .. 45 Escaped Names .. 45 Scope Rules .. 45 Numbers ..46 Integer Numbers .. 46 Real Numbers .. 464 Data Types and Objects .. 49 Integer Numbers .. 50 Real Numbers .. 50 Converting Real Numbers to Integer Numbers .. 51 Parameters .. 51 Specifying a Parameter Type .. 52 Specifying Permissible Values .. 53 Natures .. 54 Declaring a Base Nature.

7 55 Disciplines .. 57 Binding Natures with Potential and Flow .. 58 Compatibility of Disciplines .. 59 Net Disciplines ..62 Named Branches .. 64 Implicit Branches .. 645 Statements for the Analog Block.. 67 Assignment Statements .. 67 Cadence Verilog -A Language ReferenceNovember 20045 Product Version Assignment Statements in the Analog Block .. 68 Branch Contribution Statement .. 68 Indirect Branch Assignment Statement .. 70 Sequential Block Statement .. 71 Conditional Statement .. 72 Case Statement .. 72 Repeat Statement .. 73 While Statement.

8 74 For Statement .. 74 Generate Statement .. 756 Operators for Analog Blocks .. 79 Overview of Operators .. 80 Unary Operators .. 81 Binary Operators .. 81 Bitwise Operators .. 84 Ternary Operator .. 85 Operator Precedence .. 86 Expression Short-Circuiting .. 867 Built-In Mathematical Functions .. 87 Standard Mathematical Functions .. 88 Trigonometric and Hyperbolic Functions .. 88 Controlling How Math Domain Errors Are Handled .. 898 Detecting and Using Analog Events.. 91 Detecting and Using Events .. 92 Initial_step Event .. 93 Final_step Event.

9 93 Cross Event .. 94 Above Event .. 95 Cadence Verilog -A Language ReferenceNovember 20046 Product Version Event .. 979 Simulator Functions .. 99 Announcing Discontinuity .. 101 Bounding the Time Step .. 103 Finding When a Signal Is Zero .. 103 Querying the Simulation Environment .. 104 Obtaining the Current Simulation Time .. 105 Obtaining the Current Ambient Temperature .. 105 Obtaining the Thermal Voltage .. 106 Detecting Parameter Overrides .. 106 Obtaining and Setting Signal Values .. 106 Accessing Attributes .. 108 Analysis-Dependent Functions.

10 109 Determining the Current Analysis Type .. 109 Implementing Small-Signal AC Sources .. 111 Implementing Small-Signal Noise Sources .. 111 Generating Random Numbers .. 113 Generating Random Numbers in Specified Distributions .. 113 Uniform Distribution .. 114 Normal (Gaussian) Distribution .. 115 Exponential Distribution .. 115 Poisson Distribution .. 116 Chi-Square Distribution .. 117 Student s T Distribution .. 117 Erlang Distribution .. 118 Interpolating with Table Models .. 119 Analog Operators .. 120 Restrictions on Using Analog Operators.