Cadence Verilog -A Language Reference

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4 27 Signal-Flow Systems .. 27 Mixed Conservative and Signal-Flow Systems .. 27 Simulator Flow .. 282 Creating Modules.. 31 Overview .. 32 Declaring Modules .. 32 Declaring the Module Interface .. 33 Module Name .. 34 Ports .. 34 Parameters .. 36 Defining Module Analog Behavior .. 37 Defining Analog Behavior with Control Flow .. 38 Using Integration and Differentiation with Analog Signals .. 39 Using Internal Nodes in Modules .. 40 Using Internal Nodes in Behavioral Definitions .. 40 Using Internal Nodes in Higher Order Systems .. 41 ContentsCadence Verilog -A Language ReferenceNovember 20044 Product Version Modules with Netlists .. 423 Lexical Conventions .. 43 White Space ..44 Comments ..44 Identifiers .. 44 Ordinary Identifiers .. 45 Escaped Names .. 45 Scope Rules.

5 45 Numbers ..46 Integer Numbers .. 46 Real Numbers .. 464 Data Types and Objects .. 49 Integer Numbers .. 50 Real Numbers .. 50 Converting Real Numbers to Integer Numbers .. 51 Parameters .. 51 Specifying a Parameter Type .. 52 Specifying Permissible Values .. 53 Natures .. 54 Declaring a Base Nature .. 55 Disciplines .. 57 Binding Natures with Potential and Flow .. 58 Compatibility of Disciplines .. 59 Net Disciplines ..62 Named Branches .. 64 Implicit Branches .. 645 Statements for the Analog Block.. 67 Assignment Statements .. 67 Cadence Verilog -A Language ReferenceNovember 20045 Product Version Assignment Statements in the Analog Block .. 68 Branch Contribution Statement .. 68 Indirect Branch Assignment Statement .. 70 Sequential Block Statement .. 71 Conditional Statement.

6 72 Case Statement .. 72 Repeat Statement .. 73 While Statement .. 74 For Statement .. 74 Generate Statement .. 756 Operators for Analog Blocks .. 79 Overview of Operators .. 80 Unary Operators .. 81 Binary Operators .. 81 Bitwise Operators .. 84 Ternary Operator .. 85 Operator Precedence .. 86 Expression Short-Circuiting .. 867 Built-In Mathematical Functions .. 87 Standard Mathematical Functions .. 88 Trigonometric and Hyperbolic Functions .. 88 Controlling How Math Domain Errors Are Handled .. 898 Detecting and Using Analog Events.. 91 Detecting and Using Events .. 92 Initial_step Event .. 93 Final_step Event .. 93 Cross Event .. 94 Above Event .. 95 Cadence Verilog -A Language ReferenceNovember 20046 Product Version Event .. 979 Simulator Functions .. 99 Announcing Discontinuity.

7 101 Bounding the Time Step .. 103 Finding When a Signal Is Zero .. 103 Querying the Simulation Environment .. 104 Obtaining the Current Simulation Time .. 105 Obtaining the Current Ambient Temperature .. 105 Obtaining the Thermal Voltage .. 106 Detecting Parameter Overrides .. 106 Obtaining and Setting Signal Values .. 106 Accessing Attributes .. 108 Analysis-Dependent Functions .. 109 Determining the Current Analysis Type .. 109 Implementing Small-Signal AC Sources .. 111 Implementing Small-Signal Noise Sources .. 111 Generating Random Numbers .. 113 Generating Random Numbers in Specified Distributions .. 113 Uniform Distribution .. 114 Normal (Gaussian) Distribution .. 115 Exponential Distribution .. 115 Poisson Distribution .. 116 Chi-Square Distribution .. 117 Student s T Distribution.

8 117 Erlang Distribution .. 118 Interpolating with Table Models .. 119 Analog Operators .. 120 Restrictions on Using Analog Operators .. 121 Limited Exponential Function .. 121 Time Derivative Operator .. 122 Time Integral Operator .. 122 Circular Integrator Operator .. 124 Delay Operator .. 126 Cadence Verilog -A Language ReferenceNovember 20047 Product Version Filter .. 127 Slew Filter .. 130 Implementing Laplace Transform S-Domain Filters .. 132 Implementing Z-Transform Filters .. 137 Displaying Results .. 141$strobe .. 142$display .. 145$write .. 145 Specifying Power Consumption .. 145 Working with Files .. 146 Opening a File .. 146 Reading from a File .. 149 Writing to a File .. 150 Closing a File .. 151 Exiting to the Operating System .. 151 Entering Interactive Tcl Mode.

9 152 User-Defined Functions .. 153 Declaring an Analog User-Defined Function .. 153 Calling a User-Defined Analog Function .. 15410 Instantiating Modules and Primitives.. 157 Instantiating Verilog -A Modules .. 158 Creating and Naming Instances .. 158 Mapping Instance Ports to Module Ports .. 159 Connecting the Ports of Module Instances .. 160 Port Connection Rules .. 161 Overriding Parameter Values in Instances .. 161 Overriding Parameter Values from the Instantiation Statement .. 161 Instantiating Analog Primitives .. 162 Instantiating Analog Primitives that Use Array Valued Parameters .. 163 Instantiating Modules that Use Unsupported Parameter Types .. 163 Using Inherited Ports .. 164 Using an m-factor (Multiplicity Factor) .. 165 Accessing an Inherited m-factor .. 165 Cadence Verilog -A Language ReferenceNovember 20048 Product Version : Using an m-factor.

10 16511 Controlling the Compiler .. 167 Using Compiler Directives .. 168 Implementing Text Macros .. 168`define Compiler Directive .. 168`undef Compiler Directive .. 170 Compiling Code Conditionally .. 170 Including Files at Compilation Time .. 170 Setting Default Rise and Fall Times .. 171 Resetting Directives to Default Values .. 17112 Using an Analog HDL in Cadence Analog DesignEnvironment.. 173 Creating Cellviews Using the Cadence Analog Design Environment .. 174 Preparing a Library .. 174 Creating the Symbol View .. 177 Using Blocks .. 178 Creating an Analog HDL Cellview from a Symbol or Block .. 179 Descend Edit .. 182 Creating an Analog HDL Cellview .. 182 Creating a Symbol Cellview from an Analog HDL Cellview .. 185 Using Escaped Names in the Cadence Analog Design Environment.