Chapter 7 ARM Exceptions

1 ARM Exceptions Hsung-Pin ChangDepartment of Computer ScienceNational Chung Hsing UniversityOutlineoARM ExceptionsoEntering and Leaving an ExceptionoInstalling an exception HandleroSWI HandlersoInterrupt HandlersoReset HandlersoUndefined Instruction HandlersoPrefetchAbort HandleroData Abort HandlerARM ExceptionsoARM exception TypesoARM exception Vector TableoARM exception PrioritiesoUse of Modes and Registers by ExceptionsARM exception TypesoResetoUndefined instructionoSoftware Interrupt (SWI)oPrefetchAbortoData AbortoIRQoFIQARM Exceptions Types (Cont.)oResetnOccurs when the processor reset pin is assertedoFor signaling Power-upoFor resetting as if the processor has just powered upnSoftware resetoCan be done by branching to the reset vector (0x0000)oUndefined instructionnOccurs when the processor or coprocessors cannot recognize the currently execution instructionARM Exceptions Types (Cont.)

2 OSoftware Interrupt (SWI)nUser-defined interrupt instructionnAllow a program running in User mode to request privileged operations that are in Supervisor modeoFor example, RTOS functionsoPrefetchAbortnFetch an instruction from an illegal address, the instruction is flagged as invalidnHowever, instructions already in the pipeline continue to execute until the invalid instruction is reached and then a PrefetchAbort is Exceptions Types (Cont.)oData AbortnA data transfer instruction attempts to load or store data at an illegal addressoIRQnThe processor external interrupt request pin is asserted (LOW) and the I bit in the CPSR is clear (enable)oFIQnThe processor external fast interrupt request pin is asserted (LOW) and the F bit in the CPSR is clear (enable)Vector TableoAt the bottom of the memory mapoEach entry has only 32 bitnNot enough to contain the full code for a handlernThus, usually is a branch instructionor load pc instructionto the actual handleroExample.

3 ExceptionARM exception Vector TableResetUndefined InstructionSoftware InterruptPrefetchAbortData AbortReservedIRQFIQ0x000x040x080x0C0x100 x140x180x1 CException Vector handler(1)(2)ARM exception EventsARM exception PrioritiesUse of Modes and Registers by ExceptionsoAn exception changes the processor modeoThus, each exception handler has access to a certain subset of banked registersnIts own r13 or Stack Pointer(r13_modeor sp_mode)nIts own r14 or Link Register (r14_modeor lr_mode)nIts own Saved Program Status Register (SPSR_ mode).Register Organization in ARM StatesEntering and Leaving an ExceptionoThe Process Response to an ExceptionoReturning from an exception HandleroThe Return Address and Return InstructionThe Process Response to an ExceptionoCopies the CPSR into the SPSR for the mode in which the exception is to be the current mode, interrupt mask, and condition the appropriate CPSR mode bitsnChange to the appropriate modeoMap in the appropriate banked registers for that modeoDisable interruptsnIRQsare disabled when any exception disabled when a FIQ occurs, and on resetoSet lr_modeto the return addressnDiscuss in the next few slidesoSet the program counter to the vector addressfor the exceptionThe Process Response to an exception (Cont.)

4 OFor example, when reset, ARMnOverwrites R14_svcand SPSR_svcby copying the current values of the PC and CPSR into themnForces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR'sT bitnForces the PC to fetch the next instruction from address resumes in ARM Process Response to an exception (Cont.)R14_und = PC+4 SPSR_und= CPSRCPSR[4:0] = 0b11011 //Undefined ModeCPSR[5] = 0 // ARM stateCPSR[6] unchangedCPSR[7] = 1 // Disable IRQPC = 0x0000004 Undefined InstructionsR14_svc = unexpected SPSR_svc= unexpectedCPSR[4:0] = 0b10011 //Supervisor ModeCPSR[5] = 0 // ARM stateCPSR[6] = 1 // Disable FIQCPSR[7] = 1 // Disable IRQPC = 0x00000000 ResetThe Process Response to an exception (Cont.)R14_abt = PC+4 SPSR_abt= CPSRCPSR[4:0] = 0b10111 //Abort ModeCPSR[5] = 0 CPSR[6] unchangedCPSR[7] = 1 // Disable IRQPC = 0x000000 CPrefetchAbortR14_svc = PC + 4 SPSR_svc= CPSRCPSR[4:0] = 0b10011 //Supervisor ModeCPSR[5] = 0 // ARM stateCPSR[6] unchangedCPSR[7] = 1 // Disable IRQPC = 0x00000008 Software InterruptThe Process Response to an exception (Cont.)

5 R14_abt = PC+4 SPSR_abt= CPSRCPSR[4:0] = 0b10010 //Abort ModeCPSR[5] = 0 CPSR[6] unchangedCPSR[7] = 1 // Disable IRQPC = 0x0000018 Interrupt RequestR14_abt = PC + 8 SPSR_abt= CPSRCPSR[4:0] = 0b10111 //Abort ModeCPSR[5] = 0 // ARM stateCPSR[6] unchangedCPSR[7] = 1 // Disable IRQPC = 0x00000010 Data AbortThe Process Response to an exception (Cont.)R14_abt = PC + 4 SPSR_abt= CPSRCPSR[4:0] = 0b10010 //IRQ ModeCPSR[5] = 0 // ARM stateCPSR[6] = 1 //Disable FIQCPSR[7] = 1 // Disable IRQPC = 0x0000001 CFast Interrupt RequestReturning From an exception HandleroReturning from an exception handlernDepend on whether the exception handler uses the stack operations or notoGenerally, to return execution to the original execution placenRestore the CPSR from spsr_modenRestore the program counter using the return addressstored in lr_modeReturning From an exception Handler.

6 Simple ReturnoIf not require the destination mode registersto be restored from the stacknAbove two operations can be carried out by a data processing instructionwithoThe Sflag (bit 20) setnUpdate the CPSR flags when executing the data processing instructionnSUBS, MOVSoThe program counter as the destination registernExample: MOVS pc, lr//pc = lrReturning From an exception Handler : Complex ReturnoIf an exception handler entry code uses the stack to store registers nMust be preserved while handling the exceptionoTo return from such an exception handler, the stored register must be restored from the stacknReturn by a load multiple instructionwith ^qualifiernFor example: LDMFD sp!, {r0-r12,pc}^Returning From an exception HandleroNote, do not need to return from the reset handlernThe reset handler executes your maincode directlyoThe actual location when an exception is taken depends on the exception typenThe return address may not necessarily be the next instruction pointed to by the pcReturning from SWI and Undefined Instruction HandlersoSWI and undefined instruction Exceptions are generated by the instruction itselfnlr_mode= pc + 4//next instructionoRestoring the program counternIf not using stack: MOVS pc, lr//pc = lrnIf using stack to store the return addressSTMFD sp!

7 , {reglist, lr}//when entering the sp!, {reglist, pc}^//when leaving the handlerReturning from FIQ and IRQoFIQ and IRQ are generated only after the execution of an instructionnThe program counter has been updatednlr_mode= PC + 4oPoint to one instruction beyond the end of the instruction in which the exception occurredPCFIQ or IRQ occursPC+4 Returning from FIQ and IRQ (Cont.)oRestoring the program counternIf not using stack: SUBS pc, lr, #4//pc = lr-4nIf using stack to store the return addressSUB lr, lr, #4//when entering the handlerSTMFD sp!, {reglist, lr}..LDMFD sp!, {reglist, pc}^//when leaving the handlerReturn from PrefetchAbort oIf the processor supports MMU (Memory Management Unit)nThe exception handler loads the unmapped instruction into physical memory nThen, uses the MMU to map the virtual memory location into the physical one.

8 OAfter that, the handler must return to retry the instruction that caused the , the lr_ABTpoints to the instruction at the address followingthe one that caused the abort exceptionReturn from PrefetchAbort (Cont.)oSo the address to be restored is at lr_ABT 4oThus, with simple returnSUBS pc,lr,#4oIn contrast, with complex returnSUB lr,lr,#4;handler entry codeSTMFD sp!,{reglist,lr};..LDMFD sp!,{reglist,pc}^; handler exit codeReturn from Data Abortolr_ABTpoints two instructions beyondthe instruction that caused the abortnSince when a load or store instruction tries to access memory, the program counter has been , the instruction caused the data abort exception is at lr_ABT 8oSo the address to be restored is at lr_ABT 8 Return from Data Abort (Cont.)oSo the address to be restored is at lr_ABT 8oThus, with simple returnSUBS pc,lr,#8oIn contrast, with complex returnSUB lr,lr,#8;handler entry codeSTMFD sp!

9 ,{reglist,lr};..LDMFD sp!,{reglist,pc}^; handler exit is the address of the BL/SWI/Undefined Instruction fetch which had the is the address of the instruction which did not get executed since the FIQ or IRQ took is the address of the Load or Store instruction which generated the data value saved in R14_svc upon reset is an exception HandleroAny new exception handler must be installed in the vector tableoException handlers can be installed in two waysnBranch instruction: simple but have one limitationoBranch instruction only has a range of 32 MB relative to the pcnLoad pc instruction: set pc byoLoad instruction to load the handler address into the program counterInstall an exception Handler: Method 1 Vector_Init_Blockb Reset_Addrb Undefined_Addrb SWI_Addrb Prefetch_Addrb Abort_AddrNOP;Reserved vectorb IRQ_Addrb an exception Handler: Method 2 Vector_Init_BlockLDR PC, Reset_AddrLDR PC, Undefined_AddrLDR PC, SWI_AddrLDR PC, Prefetch_AddrLDR PC, Abort_AddrNOP ;Reserved vectorLDR PC, IRQ_AddrLDR PC, FIQ_AddrReset_AddrDCD Start_BootUndefined_AddrDCD Undefined_HandlerSWI_AddrDCD SWI_HandlerPrefetch_AddrDCD Prefetch_HandlerAbort_AddrDCD Abort_HandlerDCD 0 ;Reserved vectorIRQ_AddrDCD IRQ_HandlerFIQ_AddrDCDFIQ_HandlerDCDoAll ocates one or more words of memory, aligned on 4-byte boundaries, and defines the initial runtime contents of the memoryoExamplesdata1 DCD 1,5,20; defines 3 words containing; decimal values 1, 5, and 20data2 DCD mem06 + 4; defines 1 word containing 4 +.

10 The address of the label mem06 SWI HandlersoTop-Level SWI HandlersoSWI Routine in Assembly LanguageoSWI Routine in CoHow to Pass Values in and out of a SWI RoutineoCalling SWIsfrom an ApplicationSWI HandlersoWhen the SWI handler is entered, it must know which SWI is being callednThe SWI number is stored in bits 0-23 of the instructionnOr passed in an integer register, usually one of r0-r3 Top-Level SWI HandlersoBecause SVC only has its own LR_svcand SP_svcnSave all other r0~r12to the stackoTo calculate the SWI numbernCalculate the instruction address causing the SWIoSince lr_SVCholds the address of the instruction that follows the SWI instruction, thusoLDR r0, [lr, #-4]; derive the SWI instruction s addressnThe SWI number is extracted by clearing the top eight bits of the opcode:oBIC r0, r0, #0xFF000000 Top-Level SWI Handlers (Cont.)