CM1213 - 6 and 8-Channel Low Capacitance ESD Protection Arrays

1 Semiconductor Components Industries, LLC, 2013 June, 2013 Rev. 51 Publication Order Number: CM1213 /DCM12136 and 8-ChannelLow Capacitance ESDP rotection ArraysProduct DescriptionThe CM1213 family of diode Arrays has been designed to provideESD Protection for electronic components or sub systems requiringminimal capacitive loading. These devices are ideal for protectingsystems with high data and clock rates or for circuits requiring lowcapacitive loading. Each ESD channel consists of a pair of diodes inseries which steer the positive or negative ESD current pulse to eitherthe positive (VP) or negative (VN) supply rail. A Zener diode isembedded between VP and VN, offering two advantages. First, itprotects the VCC rail against ESD strikes, and second, it eliminates theneed for a bypass capacitor that would otherwise be needed forabsorbing positive ESD strikes to ground.

2 The CM1213 will protectagainst ESD pulses up to 8 kV per the IEC 61000 4 2 devices are particularly well suited for protecting systemsusing high speed ports such as , IEEE1394 (Firewire ,iLinkt), Serial ATA, DVI, HDMI and corresponding ports inremovable storage, digital camcorders, DVD RW drives and otherapplications where extremely low loading Capacitance with ESDprotection are required in a small package 6 or 8 Channels of ESD Protection Note: For 1, 2, and 4 channel Devices, See the CM1213A Datasheet Provides ESD Protection to IEC61000 4 2 Level 4 8 kV Contact Discharge Low channel Input Capacitance of pF Typical Minimal Capacitance Change with Temperature and Voltage channel Input Capacitance Matching of pF Typical is Ideal forDifferential Signals Mutual Capacitance between Signal Pin and Adjacent Signal Pin pF Typical Zener Diode Protects Supply Rail and Eliminates the Need forExternal By pass Capacitors Each I/O Pin Can Withstand Over 1000 ESD Strikes* Available in SOIC and MSOP These Devices are Pb Free and are RoHS CompliantApplications Ports at 480 Mbps in Desktop PCs, Notebooksand Peripherals IEEE1394 Firewire Ports at 400 Mbps / 800 Mbps DVI Ports.

3 HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,LCD Displays Serial ATA Ports in Desktop PCs and Hard Disk Drives PCI Express Ports General Purpose High speed Data Line ESD Protection Handheld PCs/PDAs*Standard test condition is IEC61000 4 2 level 4 test circuit with each pin subjected to 8 kV contact discharge for 1000 pulses. Dischargesare timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard productiontest to verify that all of the tested parameters are within spec after the 1000 10(Pb Free)DevicePackageShipping ORDERING INFORMATIONSOIC 8SM SUFFIXCASE 751 ACBLOCK 06 SMSOIC 8(Pb Free)2500/Tape & ReelCH6 VPVNCH5 CH4CH1 CH2CH3CM1213 06 SMCM1213 06 MRCM1213 08 MRCH8 VPVNCH2CH1CH4CH3CH7CH6 CH5 MSOP 8(Pb Free)4000/Tape & ReelCM1213 06MR4000/Tape & ReelCM1213 08 MRMSOP 8MR SUFFIXCASE 846 ADMSOP 10MR SUFFIXCASE 846AE For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011 1.

4 PIN DESCRIPTIONS6 channel , 8 Lead MSOP 8/SOIC 8 PackagesPinNameTypeDescription1CH1I/OESD Channel2CH2I/OESD Channel3 VNGNDN egative voltage supply rail4CH3I/OESD Channel5CH4I/OESD Channel6CH5I/OESD Channel7 VPPWRP ositive voltage supply rail8CH6I/OESD Channel8 channel , 10 Lead MSOP 10 PackagePinNameTypeDescription1CH1I/OESD Channel2CH2I/OESD Channel3CH3I/OESD Channel4CH4I/OESD Channel5 VNGNDN egative voltage supply rail6CH5I/OESD Channel7CH6I/OESD Channel8 VPPWRP ositive voltage supply rail9CH7I/OESD Channel10CH8I/OESD ChannelPACKAGE / PINOUT DIAGRAMSTop ViewCH1CH4 VNVP8 Lead SOIC 812348765D136 Top ViewCH1CH8 VNVP123410987D1385610 Lead MSOP 10CH2CH3CH5CH6 Top ViewCH1CH4 VNVP8 Lead MSOP 812348765D137CH2CH3CH5CH6CH2CH3CH4CH7CH6 CH5 GENERIC MARKING DIAGRAMSXXXXX= Lot NumberYY= YearWW= Work WeekD137 XXXXXYYWWD138 XXXXXYYWWCM1213 06 MRCM1213 08 MRCM1213 06 SMD136 YYWWXXXXCM1213 2.

5 ABSOLUTE MAXIMUM RATINGSP arameterRatingUnitsOperating Supply Voltage (VP VN) Temperature Range 40 to +85 CStorage Temperature Range 65 to +150 CDC Voltage at any channel input(VN ) to (VP + )VStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above theRecommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affectdevice 3. STANDARD OPERATING CONDITIONSP arameterRatingUnitsOperating Temperature Range 40 to +85 CPackage Power RatingMSOP 8 Package ( CM1213 06MR)MSOP 10 Package ( CM1213 08MR)SOIC 8 Package ( CM1213 06SM)400400600mWTable 4. ELECTRICAL OPERATING CHARACTERISTICS (Note 1)SymbolParameterConditionsMinTypMaxUnit sVPOperating Supply Voltage (VP VN) Supply Current(VP VN) = Forward VoltageTop DiodeBottom DiodeIF = 8 mA; TA = 25 Leakage CurrentTA = 25 C.

6 VP = 5 V, VN = 0 V Input CapacitanceAt 1 MHz, VP = V, VN = 0 V, VIN = Input Capacitance MatchingAt 1 MHz, VP = V, VN = 0 V, VIN = Capacitance between signal pinand adjacent signal pinAt 1 MHz, VP = V, VN = 0 V, VIN = ProtectionPeak Discharge Voltage at anychannel input, in systemContact discharge perIEC 61000 4 2 standardTA = 25 C (Notes 3 and 4) 8kVVCLC hannel Clamp VoltagePositive TransientsNegative TransientsTA = 25 C, IPP = 1 A, tP = 8/20 mS(Note 4)+ ResistancePositive TransientsNegative TransientsIPP = 1 A, tP = 8/20 mSAny I/O pin to Ground (Note 4) All parameters specified at TA = 40 C to +85 C unless otherwise Human Body Model per MIL STD 883, Method 3015, CDischarge = 100 pF, RDischarge = KW, VP = V, VN Standard IEC 61000 4 2 with CDischarge = 150 pF, RDischarge = 330 W, VP = V, VN These measurements performed with no external capacitor on VP (VP floating).

7 CM1213 INFORMATIONI nput channel Capacitance Performance CurvesFigure 1. Typical Variation of CIN vs. VIN(f = 1 MHz, VP = V, VN = 0 V, mF Chip Capacitor between VP and VN, 255C)Figure 2. Typical Variation of CIN vs. Temp(f = 1 MHz, VIN = 30 mV, VP = V, VN = 0 V, mF Chip Capacitor between VP and VN) CM1213 INFORMATION (Cont d)Typical Filter Performance (Nominal Conditions unless Specified Otherwise, 50 Ohm Environment)Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP= V)Figure 4. Insertion Loss (S21) vs. Frequency ( V DC Bias, VP= V) CM1213 INFORMATIOND esign ConsiderationsIn order to realize the maximum Protection against ESD pulses, care must be taken in the PCB layout to minimize parasiticseries inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typicallya connector) and the ESD Protection device.

8 Refer to Application of Positive ESD Pulse between Input channel and Ground,which illustrates an example of a positive ESD pulse striking an input channel . The parasitic series inductance back to powersupply is represented by L1 and L2. The voltage VCL on the line being protected is: VCL = Fwd voltage drop of D1 + VSUPPLY + L1 x d(IESD ) / dt + L2 x d(IESD ) / dtwhere IESD is the ESD current pulse, and VSUPPLY is the positive supply ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact dischargeper the IEC61000 4 2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can beapproximated by DIESD/Dt, or 30/(1x10 9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 Vincrement in VCL!

9 Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drasticallyincreased negative voltage on the line being CM1213 has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductanceL2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially whenVP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a mF ceramic chipcapacitor be connected between VP and the ground a general rule, the ESD Protection array should be located as close as possible to the point of entry of expectedelectrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the ProtectionArray as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and theESD device to minimize stray series InformationSee also ON Semiconductor Application Note, Design Considerations for ESD Protection , in the Applications section.

10 POSITIVE SUPPLY RAILCHANNELINPUTGROUND RAILCHASSIS GROUNDSYSTEM ORCIRCUITRYBEINGPROTECTEDLINE mFPATH OF ESD CURRENT PULSE IESO0 A25 AFigure 5. Application of Positive ESD Pulse between Input channel and GroundCM1213 DIMENSIONS SOIC 8 EPCASE 751 ACISSUE B ONE2 X8 XTOP VIEWSIDE VIEWBOTTOM VIEWDETAIL AEND VIEWSECTION A A8 :1. DIMENSIONS AND TOLERANCING PERASME , DIMENSIONS IN MILLIMETERS (ANGLESIN DEGREES).3. DIMENSION b DOES NOT INCLUDEDAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL MM TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM DATUMS A AND B TO BE DETERMINEDAT DATUM PLANE 8 hAADETAIL A(b) (L1) BSC__A1*For additional information on our Pb Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, FOOTPRINT* mminches SCALE 6 DIMENSIONSMSOP 8, 3x3 CASE 846 ADISSUE OE1EA2A1ebDcATOP VIEWSIDE VIEWEND VIEWL1L2 LDETAIL ADETAIL ANotes:(1) All dimensions are in millimeters.