CMOS VLSI DESIGN - RIT - People

1 cmos vlsi DESIGN . ROCHESTER INSTITUTE OF TECHNOLOGY. MICROELECTRONIC ENGINEERING. cmos vlsi DESIGN . Dr. Lynn Fuller Webpage: ~lffeee Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604. Tel (585) 475-2035. Fax (585) 475-5041. Email: Department webpage: Rochester Institute of Technology Microelectronic Engineering 12-31-2007 December 31, 2007 Dr. Lynn Fuller Page 1. cmos vlsi DESIGN . OUTLINE. DESIGN Approach Process Technology MOSIS DESIGN Rules Primitive Cells, Basic Cells, Macro Cells Projects Maskmaking References Homework Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 2. cmos vlsi DESIGN . THE NEED FOR CAD. With millions of transistors per chip it is impossible to DESIGN with no errors without computers to check layout, circuit performance, process DESIGN , etc.

2 Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 3. cmos vlsi DESIGN . COMPARISON OF DESIGN METHODOLOGIES. Full Custom DESIGN Direct control of layout and device parameters Longer DESIGN time but faster operation more dense Standard Cell DESIGN Easier to implement Limited cell library selections Gate Array or Programmable Logic Array DESIGN Fastest DESIGN turn around Reduced Performance Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 4. cmos vlsi DESIGN . STAGES IN THE CAD PROCESS. Problem Specification Behavioral DESIGN Functional and Logic DESIGN Circuit DESIGN Physical DESIGN (Layout). Fabrication Technology CAD (TCAD). Packaging Testing Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr.

3 Lynn Fuller Page 5. cmos vlsi DESIGN . DESIGN HEIRARCHY - LEVELS OF ABSTRACTION. A=B+C Behavioral Model if (A) then X: = Y. ALU RAM Block-Functional Model Gate-Level Model Transistor level Model Geometric Model Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 6. cmos vlsi DESIGN . PROCESS SELECTION. It is not necessary to know all process details to do cmos . integrated circuit DESIGN . However the process determines important circuit parameters such as supply voltage and maximum frequency of operation. It also determines if devices other than PMOS and NMOS transistors can be realized such as poly-to-poly capacitors and EEPROM transistors. The number of metal interconnect layers is also part of the process definition. Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr.

4 Lynn Fuller Page 7. cmos vlsi DESIGN . RIT SUB cmos . RIT Sub cmos . 150 mm wafers Nsub = 1E15 cm-3. Nn-well = 3E16 cm-3 L. Xj = m Np-well = 1E16 cm-3. Xj = m LOCOS. Field Ox = 6000 Long Xox = 150 Channel Lmin= m Behavior LDD/Side Wall Spacers Vdd = 5 Volts, Vto= +/- 1 Volt Two Layer Metal Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 8. cmos vlsi DESIGN . RIT SUB cmos . NMOSFET PMOSFET. N+ Poly m Aluminum 6000 . Field Oxide N+ D/S LDD P+ D/S n+ well p+ well LDD contact contact P-well N-well Channel Stop N-type Substrate 10 ohm-cm Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 9. cmos vlsi DESIGN . RIT ADVANCED cmos VER 150. RIT Advanced cmos . 150 mm Wafers Nsub = 1E15 cm-3 or 10 ohm-cm, p Nn-well = 1E17 cm-3 L.

5 Xj = m Np-well = 1E17 cm-3. Xj = m Shallow Trench Isolation Field Ox (Trench Fill) = 4000 Long Dual Doped Gate n+ and p+ Channel Xox = 100 Behavior Lmin = m , Lpoly = m, Leff = m LDD/Nitride Side Wall Spacers Vdd = volts TiSi2 Salicide Tungsten Plugs, CMP, 2 Layers Aluminum Vto=+- volts Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 10. cmos vlsi DESIGN . RIT ADVANCED cmos . NMOSFET PMOSFET. N+ Poly P+ Poly N+ D/S P+ D/S. p+ well n+ well contact contact LDD. P-well N-well LDD. Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 11. cmos vlsi DESIGN . LAMBDA, Lmin, Ldrawn, Lmask, Lpoly, Lint, Leff, L. Lambda = DESIGN rule parameter, , ie m Ldrawn Lmin = min drawn poly length, 2 m Lmask Lmask = ?

6 Depends on +/-bias m x 5. Lpoly Lresist after photo (resist trimming??) m Gate Lpoly after poly etch m Source at 0 V Lpoly after poly reoxidation m Drain at m Lint m Leff m L Ldrawn = what was drawn Internal Channel Length, Lint =distance between junctions, including under diffusion Effective Channel Length, Leff = distance between space charge layers,Vd = Vs= 0. Channel Length,Rochester L, = Institute distance between space charge layers, when Vd= what it is of Technology Extracted Channel Length Parameters = anything that makes the fit good (not real). Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 12. cmos vlsi DESIGN . MOSIS TSMC 2 POLY 4 METAL PROCESS. #tech-codes Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr.

7 Lynn Fuller Page 13. cmos vlsi DESIGN . MOSIS TSMC 2-POLY 4-METAL LAYERS. MASK MENTOR GDS COMMENT. LAYER NAME NAME #. N WELL 42. ACTIVE 43. POLY 46. N PLUS 45. P PLUS 44. CONTACT 25 48. 47. METAL1 49. VIA 50. METAL2 51. Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 14. cmos vlsi DESIGN . MORE LAYERS USED IN MASK MAKING. LAYER NAME GDS COMMENT. 70 Not used alignment 81 Placed on first level mask nw_res 82 Placed on nwell level mask active_lettering 83 Placed on active mask channel_stop 84 Overlay/Resolution for Stop Mask pmos_vt 85 Overlay/Resolution for Vt Mask LDD 86 Overlay/Resolution for LDD Masks p plus 87 Overlay/Resolution for P+ Mask n plus 88 Overlay/Resolution for N+ Mask Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr.

8 Lynn Fuller Page 15. cmos vlsi DESIGN . OTHER LAYERS. DESIGN Layers Other DESIGN Layers 81. N-WELL (42) P+ Resolution (87) 43. ACTIVE (43) STI Resolution (82). POLY (46) Stop Resolution (84) STI. P-SELECT (44) Vt Resolution (85). N-SELECT (45) 85 Active Resolution (83). CC (25) N+ Resolution (88) 46 44. METAL 1 (49) 49. VIA (50) 45. 42. METAL 2 (51). 84 Nmos Vt 87 Poly 88 25. Active 83 Rochester Institute of Technology Stop Microelectronic Engineering P+ N+. December 31, 2007 Dr. Lynn Fuller Page 16. cmos vlsi DESIGN . LAMBDA BASED DESIGN RULES. The DESIGN rules may change from foundry to foundry or for different technologies. So to make the DESIGN rules generic the sizes, separations and overlap are given in terms of numbers of lambda ( ). The actual size is found by multiplying the number by the value for lambda.

9 For example: RIT PMOS process = 10 m and minimum metal width is 3 so that gives a minimum metal width of 30 m. The RIT. cmos process (single well) has = 4 m and the minimum metal width is also 3 so minimum metal is 12 m but if we send our cmos designs out to industry might be m so the minimum metal of 3 corresponds to m. In all cases the DESIGN rule is the minimum metal width = 3 . Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 17. cmos vlsi DESIGN . LAYOUT RULES. Perfect Overlay Slight Overlay Misalignment Not Fatal Fatal Layout rules prevent slight misalignment from being fatal. Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 18. cmos vlsi DESIGN . MOSIS LAMBDA BASED DESIGN RULES.

10 Well Active in p-well Poly 1. 10 6 3. Active 3 n+ n+. p+ Poly 2. 5 2. Diff 3 Poly 9 Same well edge Potential Potential n-Substrate 5 3 3. (Outside well) 2. p+ n+. active 1 3 contact to poly metal 2 1. 2. 3. 2. 2. 3. 2 2. 1. 2 p select If = 1 m then contact is 1. 2 m x 2 m Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 19. cmos vlsi DESIGN . MOSIS LAMBDA BASED DESIGN RULES. metal two 2. 1. MOSIS Educational Program 3. 2. 4 Instructional Processes Include: 1. AMI = m SCMOS Rules 1. AMI = m SCMOS Rules Research Processes: go down to poly length of 65nm Rochester Institute of Technology Microelectronic Engineering December 31, 2007 Dr. Lynn Fuller Page 20. cmos vlsi DESIGN . MOSIS REQUIREMENTS. MOSIS requires that projects have successfully passed LVS (Layout Versus Schematic) and DRC ( DESIGN Rule Checking).