Computer Architecture - Introduction

1 1 Computer Architecture -IntroductionChin-FuKuo2 About This Course Textbook J. L. Hennessy and D. A. Patterson, ComputerArchitecture: A Quantitative Approach, 3rd Edition,Morgan Kaufmann Publishing Co., 2002. Course Grading 30% Project and Quiz 35% Mid-term Examination 35% Final-term Examination 5~10% Class Participation & Discussion3 This Is an Advanced Course Have you taken Computer organization before? If you never took Computer organization before You MUST take it if you are an undergraduate student; You may still take this course if you insist, but be prepared towork hard and read some chapters in Computer Organizationand Design (COD)3/e 4 Reference Resources Patterson, UC-Berkeley Spring 2001 ~pattrsn/252S01/ David E.

2 Culler, UC-Berkeley, Spring 2002 ~culler/cs252-s02/ David E. Culler, UC-Berkeley, Spring 2005 ~culler/courses/cs252-s05/ Many slides in this course were adapted from UC Berkeley sCS252 Course. Copyright 2005, UC What is Computer Architecture ? Fundamental Abstractions & Concepts Instruction Set Architecture & organization Why Take This Course? Technology Performance Computer Architecture Renaissance6 What is Computer Architecture ?ApplicationsInstruction SetArchitecture (ISA)CompilerOperatingSystemFirmware Coordination of manylevels of abstraction Under a rapidlychanging set of forces Design, Measurement,andEvaluationI/O systemInstr. Set DesignCircuit DesignDatapath& ControlLayout &fabSemiconductor Materials7 Outline What is Computer Architecture ?

3 Fundamental Abstractions & Concepts Instruction Set Architecture & organization Why Take This Course? Technology Performance Computer Architecture Renaissance8 The Instruction Set: a Critical Interfaceinstruction setSoftware (SW)Hardware (HW) Properties of a good abstraction Lasts through many generations (portability) Used in many different ways (generality) Providesconvenientfunctionality to higher levels Permits anefficientimplementation at lower levels9 Instruction Set the attributes of a [computing] system as seen by theprogrammer, the conceptual structure and functionalbehavior, as distinct from the organization of the dataflows and controls the logic design, and the physicalimplementation.

4 Amdahl,Blaaw, and Brooks, 1964 SOFTWARESOFTWARE-- organization of Programmable Storage--Data Types & Data Structures:Encodings & Representations--Instruction Formats--Instruction (or Operation Code) Set--Modes of Addressing and Accessing Data Items and Instructions--Exceptional Conditions10 Computer (Machine) OrganizationLogic Designer's ViewISA LevelFUs& Interconnect Capabilities & Performance Characteristics ofPrincipal Functional Units (FUs) (Registers, ALU, Shifters, Logic Units, ..) Ways in which these components areinterconnected(Bus, Network,..) Information flows between components(Data,Messages, Packets, Data path) Logic and means by which such informationflow is controlled(Controller, Protocol handler,Control path, Microcode) Choreography ofFUsto realize the ISA(Execution, Architectural description) Register Transfer Level (RTL) Description(Implementation description)

5 11 Fundamental Execution CycleInstructionFetchInstructionDecodeOp erandFetchExecuteResultStoreNextInstruct ionObtain instructionfrom programstorageDetermine requiredactions andinstruction sizeLocate and obtainoperand dataCompute result valueor statusDeposit results instorage for lateruseDetermine of an ISA Set of machine-recognized data types bytes, words, integers, floating point, strings, .. Operations performed on those data types Add, sub,mul, div,xor, move,.. Programmable storage regs, PC, memory Methods of identifying and obtaining data referenced by instructions(addressing modes) Literal, reg., absolute, relative,reg+ offset,.. Format (encoding) of the instructions Op code, operand fields.

6 Current Logical Stateof the MachineNext Logical Stateof the Machine13 Computer as a State Machine State: defined by storage Registers, Memory, Disk,.. Next state is influenced by the operation Instructions, I/O events, interrupts,.. When is the next state decided? Result Store: Register write, Memory write Output: Device (disk, network) writeCurrent Logical Stateof the MachineNext Logical Stateof the Machine14 Time for a Long Break and Partner w/ a classmate who you didn t know Get the following information from your partner: Personal Information & Interests:Name, Department, Hometown, Favorite sports,.. Research Directions:Research Lab, Advisor, Projects.

7 Career Plan:Engineer, Manager, Teacher,.. Why take this course Introduce your partner to the class after the : MIPS R30000r0r1 r31 PClohiProgrammable storage2^32 xbytes31 x 32-bitGPRs(R0=0)32 x 32-bit FPregs(paired DP)HI, LO, PCData types ?Format ?Addressing Modes?Arithmetic logicalAdd,AddU, Sub,SubU, And, Or,Xor, Nor, SLT, SLTU,AddI,AddIU, SLTI, SLTIU,AndI,OrI,XorI,LUISLL, SRL, SRA, SLLV, SRLV, SRAVM emory AccessLB, LBU, LH, LHU, LW, LWL,LWRSB, SH, SW, SWL, SWRC ontrolJ, JAL, JR, JALRBEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL32-bit instructions on word boundary16 Basic ISA ClassesAccumulator:1 addressadd Aacc acc +mem[A]1+x addressaddxAacc acc +mem[A+ x]Stack:0 addressaddtos tos+ nextGeneral Purpose Register:2 addressadd A BEA(A) EA(A) + EA(B)3 addressadd A B CEA(A) EA(B) + EA(C)Load/Store.

8 3 addressadd RaRbRcRa Rb+Rcload RaRbRa mem[Rb]store RaRbmem[Rb] Ra17 MIPS Addressing Modes & Formats Simple addressing modes All instructions 32 bits wideoprsrtrdimmedregisterRegister (direct)oprsrtregisterBase+index+Memoryi mmedoprsrtImmediateimmedoprsrtPCPC-relat ive+Memory Register Indirect?18 Instruction Formats & RISCV ariable:Fixed:Hybrid:.. Addressing modes each operand requiresaddessspecifier=> variable format Code size => variable length instructions Performance => fixed length instructions simple decoding, predictable operations RISC: With load/store instruction arch, only one memory addressand few addressing modes => simple format, address mode givenbyopcode(Why would RISC perform better than CISC?)

9 19 Cray-1: the Original RISCOp015 RdRs1R22689 Load, Store and Branch35Op015 RdRs1 Immediate268935150 Register-Register20 VAX-11: the Canonical CISC Rich set of orthogonal address modes immediate, offset, indexed,autoinc/dec, indirect, indirect+offset applied to any operand Simple and complex instructions synchronization instructions data structure operations (queues) polynomial evaluation1. In programming,canonicalmeans "according to the rules. 2. Acanonicalbook is considered inspired and authoritative and is a partof the rule or standard of 01nmVariable format, 2 and 3 address instruction21 Load/Store ArchitecturesMEMreg Substantial increase in instructions Decrease in data BW (due to many registers) Even more significant decrease in CPI (pipelining) Cycle time, Real estate, Design time, Design complexity 3-address GPR Register-to-register arithmetic Load and store with simple addressing modes (reg+ immediate) Simple conditionalscompare ops + branch zcompare&branchcondition code + branch on condition Simple fixed-format encodingopopoprrrrrimmedoffset22 MIPS R3000 ISA (Summary)

10 Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management SpecialR0-R31 PCHILOOPOPOP rsrtrdsafunctrsrtimmediatejump target3 Instruction Formats: all 32 bits wideRegisters23 Evolution of Instruction SetsSingle Accumulator(EDSAC 1950)Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)Separation of Programming Modelfrom ImplementationHigh-level Language Based (Stack)Concept of a Family(B5000 1963)(IBM 360 1964)General Purpose Register MachinesComplex Instruction SetsLoad/Store ArchitectureRISC(Vax, Intel 432 1977-80)(CDC 6600, Cray 1 1963-76)(MIPS,Sparc,HP-PA,IBM RS6000, 1987)iX86?