Computer Architecture - Introduction

1 1 Computer Architecture -IntroductionChin-FuKuo2 About This Course Textbook J. L. Hennessy and D. A. Patterson, ComputerArchitecture: A Quantitative Approach, 3rd Edition,Morgan Kaufmann Publishing Co., 2002. Course Grading 30% Project and Quiz 35% Mid-term Examination 35% Final-term Examination 5~10% Class Participation & Discussion3 This Is an Advanced Course Have you taken Computer Organization before? If you never took Computer Organization before You MUST take it if you are an undergraduate student; You may still take this course if you insist, but be prepared towork hard and read some chapters in Computer Organizationand design (COD)3/e 4 Reference Resources Patterson, UC-Berkeley Spring 2001 ~pattrsn/252S01/ David E. Culler, UC-Berkeley, Spring 2002 ~culler/cs252-s02/ David E. Culler, UC-Berkeley, Spring 2005 ~culler/courses/cs252-s05/ Many slides in this course were adapted from UC Berkeley sCS252 Course.

2 Copyright 2005, UC What is Computer Architecture ? Fundamental Abstractions & Concepts Instruction Set Architecture & Organization Why Take This Course? Technology Performance Computer Architecture Renaissance6 What is Computer Architecture ?ApplicationsInstruction SetArchitecture (ISA)CompilerOperatingSystemFirmware Coordination of manylevels of abstraction Under a rapidlychanging set of forces design , Measurement,andEvaluationI/O systemInstr. Set DesignCircuit DesignDatapath& ControlLayout &fabSemiconductor Materials7 Outline What is Computer Architecture ? Fundamental Abstractions & Concepts Instruction Set Architecture & Organization Why Take This Course? Technology Performance Computer Architecture Renaissance8 The Instruction Set: a Critical Interfaceinstruction setSoftware (SW)Hardware (HW) Properties of a good abstraction Lasts through many generations (portability) Used in many different ways (generality) Providesconvenientfunctionality to higher levels Permits anefficientimplementation at lower levels9 Instruction Set the attributes of a [computing] system as seen by theprogrammer, the conceptual structure and functionalbehavior, as distinct from the organization of the dataflows and controls the logic design , and the physicalimplementation.

3 Amdahl,Blaaw, and Brooks, 1964 SOFTWARESOFTWARE--Organization of Programmable Storage--Data Types & Data Structures:Encodings & Representations--Instruction Formats--Instruction (or Operation Code) Set--Modes of Addressing and Accessing Data Items and Instructions--Exceptional Conditions10 Computer (Machine) OrganizationLogic Designer's ViewISA LevelFUs& Interconnect Capabilities & Performance Characteristics ofPrincipal Functional Units (FUs) (Registers, ALU, Shifters, Logic Units, ..) Ways in which these components areinterconnected(Bus, Network,..) Information flows between components(Data,Messages, Packets, Data path) Logic and means by which such informationflow is controlled(Controller, Protocol handler,Control path, Microcode) Choreography ofFUsto realize the ISA(Execution, Architectural description) Register Transfer Level (RTL) Description(Implementation description)11 Fundamental Execution CycleInstructionFetchInstructionDecodeOp erandFetchExecuteResultStoreNextInstruct ionObtain instructionfrom programstorageDetermine requiredactions andinstruction sizeLocate and obtainoperand dataCompute result valueor statusDeposit results instorage for lateruseDetermine of an ISA Set of machine-recognized data types bytes, words, integers, floating point, strings.

4 Operations performed on those data types Add, sub,mul, div,xor, move,.. Programmable storage regs, PC, memory Methods of identifying and obtaining data referenced by instructions(addressing modes) Literal, reg., absolute, relative,reg+ offset,.. Format (encoding) of the instructions Op code, operand fields,..Current Logical Stateof the MachineNext Logical Stateof the Machine13 Computer as a State Machine State: defined by storage Registers, Memory, Disk,.. Next state is influenced by the operation Instructions, I/O events, interrupts,.. When is the next state decided? Result Store: Register write, Memory write Output: Device (disk, network) writeCurrent Logical Stateof the MachineNext Logical Stateof the Machine14 Time for a Long Break and Partner w/ a classmate who you didn t know Get the following information from your partner: Personal Information & Interests:Name, Department, Hometown, Favorite sports.

5 Research Directions:Research Lab, Advisor, Projects,.. Career Plan:Engineer, Manager, Teacher,.. Why take this course Introduce your partner to the class after the : MIPS R30000r0r1 r31 PClohiProgrammable storage2^32 xbytes31 x 32-bitGPRs(R0=0)32 x 32-bit FPregs(paired DP)HI, LO, PCData types ?Format ?Addressing Modes?Arithmetic logicalAdd,AddU, Sub,SubU, And, Or,Xor, Nor, SLT, SLTU,AddI,AddIU, SLTI, SLTIU,AndI,OrI,XorI,LUISLL, SRL, SRA, SLLV, SRLV, SRAVM emory AccessLB, LBU, LH, LHU, LW, LWL,LWRSB, SH, SW, SWL, SWRC ontrolJ, JAL, JR, JALRBEq, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL32-bit instructions on word boundary16 Basic ISA ClassesAccumulator:1 addressadd Aacc acc +mem[A]1+x addressaddxAacc acc +mem[A+ x]Stack:0 addressaddtos tos+ nextGeneral Purpose Register:2 addressadd A BEA(A) EA(A) + EA(B)3 addressadd A B CEA(A) EA(B) + EA(C)Load/Store:3 addressadd RaRbRcRa Rb+Rcload RaRbRa mem[Rb]store RaRbmem[Rb] Ra17 MIPS Addressing Modes & Formats Simple addressing modes All instructions 32 bits wideoprsrtrdimmedregisterRegister (direct)oprsrtregisterBase+index+Memoryi mmedoprsrtImmediateimmedoprsrtPCPC-relat ive+Memory Register Indirect?

6 18 Instruction Formats & RISCV ariable:Fixed:Hybrid:.. Addressing modes each operand requiresaddessspecifier=> variable format Code size => variable length instructions Performance => fixed length instructions simple decoding, predictable operations RISC: With load/store instruction arch, only one memory addressand few addressing modes => simple format, address mode givenbyopcode(Why would RISC perform better than CISC?)19 Cray-1: the Original RISCOp015 RdRs1R22689 Load, Store and Branch35Op015 RdRs1 Immediate268935150 Register-Register20 VAX-11: the Canonical CISC Rich set of orthogonal address modes immediate, offset, indexed,autoinc/dec, indirect, indirect+offset applied to any operand Simple and complex instructions synchronization instructions data structure operations (queues) polynomial evaluation1. In programming,canonicalmeans "according to the rules. 2. Acanonicalbook is considered inspired and authoritative and is a partof the rule or standard of 01nmVariable format, 2 and 3 address instruction21 Load/Store ArchitecturesMEMreg Substantial increase in instructions Decrease in data BW (due to many registers) Even more significant decrease in CPI (pipelining) Cycle time, Real estate, design time, design complexity 3-address GPR Register-to-register arithmetic Load and store with simple addressing modes (reg+ immediate) Simple conditionalscompare ops + branch zcompare&branchcondition code + branch on condition Simple fixed-format encodingopopoprrrrrimmedoffset22 MIPS R3000 ISA (Summary) Instruction Categories Load/Store Computational Jump and Branch Floating Point coprocessor Memory Management SpecialR0-R31 PCHILOOPOPOP rsrtrdsafunctrsrtimmediatejump target3 Instruction Formats.

7 All 32 bits wideRegisters23 Evolution of Instruction SetsSingle Accumulator(EDSAC 1950)Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)Separation of Programming Modelfrom ImplementationHigh-level Language Based (Stack)Concept of a Family(B5000 1963)(IBM 360 1964)General Purpose Register MachinesComplex Instruction SetsLoad/Store ArchitectureRISC(Vax, Intel 432 1977-80)(CDC 6600, Cray 1 1963-76)(MIPS,Sparc,HP-PA,IBM RS6000, 1987)iX86?24 Outline What is Computer Architecture ? Fundamental Abstractions & Concepts Instruction Set Architecture & Organization Why Take This Course? Technology Performance Computer Architecture Renaissance25 Why Take This Course? To design the next great instruction set?.. instruction set Architecture has largely converged especially in the desktop / server / laptop space dictated by powerful market forces Tremendous organizational innovation relative to established ISAabstractions Many New instruction sets or equivalent embedded space, controllers, specialized devices.

8 design , analysis, implementation concepts vital to all aspects of EE& CS systems, PL, theory, circuit design , VLSI, comm. Equip you with an intellectual toolbox for dealing with a host ofsystems design challenges26 Related CoursesComputerOrganizationComputerOrgan izationComputerArchitectureComputerArchi tectureParallel & AdvancedComputer ArchitectureParallel & AdvancedComputer ArchitectureEmbeddedSystemsSoftwareEmbed dedSystemsSoftwareHow to build it,ImplementationdetailsWhy, Analysis,EvaluationParallel Architectures,Hardware-Software InteractionsSystem OptimizationRTOS, Tools-chain,I/O & Device drivers,CompilersHardware-SoftwareCo-des ignHardware-SoftwareCo-designHow to makeembedded systems betterSoftwareSoftwareOS,Programming Lang, system ProgrammingSpecial Topics onComputer PerformanceOptimizationSpecial Topics onComputer PerformanceOptimizationPerformance tools,Performance skills,Compiler optimization tricks27 Computer Industry Desktop Computing Price-performance, Graphics performance Intel, AMD, Apple.

9 Microsoft, Linux system integrators & Retailers Servers Availability, Scalability, Throughput IBM, HP-Compaq, Sun, Intel, Microsoft, Linux Embedded Systems Application-specific performance Power, Integration28 Forces on Computer ArchitectureComputerArchitectureTechnolo gyProgrammingLanguagesOperatingSystemsHi storyApplications29 Course FocusUnderstanding the design techniques, machinestructures, technology factors, evaluationmethods that will determine the form ofcomputers in 21st CenturyTechnologyProgrammingLanguagesOpe ratingSystemsHistoryApplicationsInterfac e design (ISA)Measurement &EvaluationParallelismComputer Architecture : Instruction Set design Organization Hardware/Software BoundaryCompilers30 Outline What is Computer Architecture ? Fundamental Abstractions & Concepts Instruction Set Architecture & Organization Why Take This Course? Technology Trend Performance Computer Architecture Renaissance31 Dramatic Technology Advance Prehistory: Generations 1stTubes 2ndTransistors 3rdIntegrated Circuits Discrete advances in each generation Faster, smaller, more reliable, easier to utilize Modern computing: Moore s Law Continuous advance, fairly homogeneous technology32 Moore s Law Cramming More Components onto Integrated Circuits Gordon Moore, Electronics, 1965 # on transistors on cost-effective integrated circuit double every 18 months(IC 18 )33 Year100010000100000100000010000000100000 0001970197519801985199019952000i80386i40 04i8080 Pentiumi80486i80286i8086 Technology Trends:Microprocessor CapacityCMOS improvements: Die size: 2X every 3 yrs Line width: halve / 7 yrsItanium II: 241 millionPentium 4: 55 millionAlpha 21264: 15 millionPentium Pro: millionPowerPC 620: millionAlpha 21164.

10 MillionSparcUltra: millionMoore s Law34sizeYear100010000100000100000010000 0001000000001000000000197019751980198519 9019952000 Memory Capacity(Single Chip DRAM)yearsize(Mb) ns19861190 ns19894165 ns199216145 ns199664120 ns2000256100 ns2003102460 ns35 Optimizing the design Functional requirements set by: market sector particular company s product plan what the competition is expected to do Usual pressure to do everything minimize time to market maximize performance minimize cost & power And you only get 1 shot no time to try multiple prototypes and evolve to a polished product requires heaps of simulations to quantify everything quantify model is focus of this course requires deep infrastructure and support36 Technology Trends Integrated Circuits density increases at 35%/yr. die size increases 10%-20%/yr combination is a chip complexity growth rate of 55%/yr transistor speed increase is similar but signal propagation doesn t trackthis curve-so clock rates don t go up as fast DRAM density quadruples every 3-4 years (40-60%/yr) [4x steps] cycle time decreases slowly-33% in 10 years interface changes have improved bandwidth however Network rapid escalation-US bandwidth doubles every year at the machine theexpectation bumps periodically-gigabit ether is here now373 Categories Emerge Desktop optimized for price-performance (frequency is a red herring) Server optimized for: availability, scalability, and throughput plus a new one: power ==> cost and physical plant site Embedded fastest growing and the most diverse space washing machine controller to a network core router optimizations.