Transcription of COMPUTER ORGANIZATION AND ARCHITECTURE
1 COMPUTER ORGANIZATION AND ARCHITECTUREIII Semester (IARE -R16)Dr. Y. MOHANA ROOPA , Professor Dr. P. L. SRINIVASA MURTHY, Professor Mr. RAO, Associate Professor Ms. ,Assistant Professor COMPUTER SCIENCE AND ENGINEERINGINSTITUTE OF AERONAUTICAL ENGINEERING(Autonomous)DUNDIGAL, HYDERABAD-500 0431 Unit-1 IntroductiontoComputerOrganizationandArc hitectureBasicComputerOrganization Thebasiccomputerorganizationhasthreemain components: CPU Memorysubsystem I/OsubsystemGenericcomputerOrganizationS ystembusThesystembushasthreebuses, Addressbus Databus , : Fetch Decode ExecuteInstructioncycle Firsttheprocessorfetchesorreadstheinstru ctionfrommemory.
2 Thenitdecodestheinstructiondeterminingwh ichinstructionithasfetched. Finally,itperformstheoperationsnecessary toexecutetheinstruction. Itperformssomeoperationinternally,andsup pliestheaddress,data&controlsignalsneede dbymemory& TheREAD signalisasignalonthecontrolbuswhichthemi croprocessorassertswhenitisreadytoreadda tafrommemoryorI/Odevice. WhenREAD signalisassertedthememorysubsystemplaces theinstructioncodebefetchedontothecomput ersystem READ signalcausesthememorytoreadthedata,theWR ITE operationcausesthememorytostorethedataTi mingdiagramsMemoryreadoperation Infig(a)themicroprocessorplacestheaddres sontothebusatthebeginningofaclockcycle,a 0 ,toallowformemorytodecodetheaddressandac cessitsdata,themicroprocessorassertstheR EAD controlsignal.
3 ,themicroprocessorreadsthedataoffthesyst embusandstoresitinoneoftheregisters. Infig(b)theprocessorplacestheaddressandd ataontothesystembusduringthefirstclockpu lse. ThemicroprocessorthenassertstheWRITE controlsignalattheendofthesecondclockcyc le. (CPU)istheelectroniccircuitrywithinacomp uterthatcarriesouttheinstructionsofacomp uterprogrambyperformingthebasicarithmeti c,logical,controlandinput/output(I/O) Databusisusedtoshuffledatabetweenthevari ouscomponentsinacomputersystem. Whenthesoftwarewantstoaccesssomeparticul armemorylocationorI/Odeviceitplacestheco rrespondingaddressontheaddressbus. Theregistersection,asitsnameimplies,incl udesasetofregistersandabusorothercommuni cationmechanism.
4 The register in a processor s instruction set ARCHITECTURE are foundinthesectionoftheCPU. Thefetchportionoftheinstructioncycle, programcounter . Attheendoftheinstructionfetch,theCPUread stheinstructioncodefromthesystemdatabus. Itstoresthisvalueinaninternalregister,us uallycalledthe instructionregister .CPUO rganization Thearithmetic/logicunit(or)ALUperformsmo starithmeticandlogicoperationssuchasaddi ngandANDingvalues. CPUcontrolsthecomputer, ,whichitusedtogeneratethecontrolsignals. Thecontrolunitalsogeneratesthesignalsfor thesystemcontrolbussuchasREAD,WRITE,IO/s ignalsMemorySubsystemOrganization Memoryisthegroupofcircuitsusedtostoredat a.
5 Memorycomponentshavesomenumberofmemorylo cations,eachwordofwhichstoresabinaryvalu eofsomefixedlength. Thenumberoflocationsandthesizeofeachloca tionvaryfrommemorychiptomemorychip, Memoryisusuallyorganizedintheformofarray s,inwhicheachcelliscapableofstoringonebi tinformation. Eachrowofcellconstitutesamemoryword,anda llcellsofarowareconnectedtoacommoncolumn calledwordline,whichisdrivenbytheaddress decoderonthechipTypesofMemory Therearetwotypesofmemorychips, (ROM) (RAM)ROMC hips MaskedROM(or)simplyROM PROM(ProgrammedReadOnlyMemory) EPROM(ElectricallyProgrammedReadOnlyMemo ry) EEPROM(ElectricallyErasablePROM) FlashMemoryMaskedROM AmaskedROMorsimplyROMisprogrammedwithdat aaschipisfabricated.
6 PROM SomeROMdesignsallowthedatatobeloadedbyth euser,thusprovidingprogrammableROM(PROM) . ,the e o y o tai s all s. The use i se t s at the e ui ed lo atio s y u i goutthefuseattheselocationsusinghighcurr entpulse. ThefusesinPROM cannotrestoreoncetheyare low ,PROM s a o ly e p og a ed o e. EPROM ThechipiserasedbybeingplacedunderUVlight , EEPROM AsignificantdisadvantageoftheEPROM isthechipisphysicallyremovedfromthecircu itforreprogrammingandthatentirecontentsa reerasedbytheUVlight. AnotherversionofEPROMisEEPROM thatcanbebothprogrammedanderasedelectric ally,suchchipscalledEEPROM,donothavetore moveforerasure. TheonlydisadvantageofEEPROM isthatdifferentvoltagesareneedforerasing ,writing, RAMC hips: ThedatapinsarebidirectionalunlikeinROM.
7 AROM chiplosesitsdataoncepowerisremovedsoitis avolatilememory. RAMchipsaredifferentiatedbasedonthedatat heymaintain. DynamicRAM(DRAM) StaticRAM(SRAM)MemorychipsInternalorgani zation DynamicRAM ,chargingitsmemorycellstotheirmaximumval ues. Thechargingslowlyleaksoutandwouldeventua llygotoolowtorepresentvaliddata. Beforethisarefreshercircuitreadstheconte ntoftheDRAM andrewritesdatatoitsoriginallocations. DRAM isusedtoconstructtheRAMinpersonalcompute rs. StaticRAM ,itscontentsstayvaliditdoesnothavetobere freshed. DynamicRAM ,chargingitsmemorycellstotheirmaximumval ues. Thechargingslowlyleaksoutandwouldeventua llygotoolowtorepresentvaliddata.
8 Beforethisarefreshercircuitreadstheconte ntoftheDRAM andrewritesdatatoitsoriginallocations. Therearetwocommonlyusedorganizationsform ultibytedata. Bigendian Littleendian InBIG-ENDIAN systemsthemostsignificantbyteofamulti-by tedataitemalwayshasthelowestaddress,whil etheleastsignificantbytehasthehighestadd ress. InLITTLE-ENDIAN systems,theleastsignificantbyteofamulti- bytedataitemalwayshasthelowestaddress, Read,write,scan,etc. ThissimplifiestheCPUI nputDevice ,thebuffersareenabledanddatapassesonthed atabus. Theenablelogiccontains8- Thedesignoftheinterfacecircuitryforanout putdevicesuchasacomputermonitorissomewha tdifferentthanfortheinputdevice.
9 Tri-statebuffersarereplacedbyaregister. Thetri-statebuffersareusedininputdevicei nterfacestomakesurethatonedevicewritesda tatothebusatanytime. Sincetheoutputdevicesreadfromthebus,rath erthatwritesdatatoit,theydon t needthebuffers. Thedatacanbemadeavailabletoalloutputdevi cesbutthedevicesonlycontainsthecorrectad dresswillreaditinMultibyteorganization Therearetwocommonlyusedorganizationsform ultibytedata. Bigendian Littleendian InBIG-ENDIAN systemsthemostsignificantbyteofamulti-by tedataitemalwayshasthelowestaddress,whil etheleastsignificantbytehasthehighestadd ress. InLITTLE-ENDIAN systems,theleastsignificantbyteofamulti- bytedataitemalwayshasthelowestaddress, Thedesignoftheinterfacecircuitryforanout putdevicesuchasacomputermonitorissomewha tdifferentthanfortheinputdevice.
10 Tri-statebuffersarereplacedbyaregister. Thetri-statebuffersareusedininputdevicei nterfacestomakesurethatonedevicewritesda tatothebusatanytime. Sincetheoutputdevicesreadfromthebus,rath erthatwritesdatatoit,theydon t needthebuffers. Thedatacanbemadeavailabletoalloutputdevi cesbutthedevicesonlycontainsthecorrectad dresswillreaditinAnoutputdevice:(a)withi tsinterfaceand(b)theenablelogicforthereg istersOutputDevice :AbidirectionalI/Odevicewithitsinterface andenable/loadlogicOutputDeviceASimpleCo mputer-LevelsofPL Highlevellanguage Assemblylevellanguage Machinelevellanguage ++,JavaandFORTRAN arehighlevellanguages. :LevelsofprogramminglanguagesASimpleComp uter-LevelsofPL Highlevellanguageprogramsarecompiledanda ssemblylevellanguageprogramsareassembled .
