DAC8551 16-Bit, Ultralow-Glitch, Voltage-Output …

1 16-Bit DACVDDVOUTS hift RegisterGNDSYNCSCLKDINVREFDAC RegisterRef (+)PWD ControlResistorNetwork1616 VFBC opyright 2016, texas instruments IncorporatedProductFolderOrderNowTechnic alDocumentsTools &SoftwareSupport &CommunityReferenceDesignAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand APRIL2005 REVISEDJUNE2017 DAC855116-Bit, Ultralow-Glitch, voltage -Ou tputDigital to AnalogConverter11 Features1 RelativeAccuracy:8 LSB nV-s MicroPowerOperation:140 A at V Power-OnResetto Zero V to V 16-BitMonotonic SettlingTime:10 s to Low-PowerSerialInterfacewithSchmitt-Trig geredInputs On-ChipOutputBufferAmplifierwithRail-to- RailOperation Power-DownCapability BinaryInput SYNCI nterruptFacility Drop-InCompatibleWithDAC85x1and DAC8550(2's ComplementInput)2 Applications ProcessControl DataAcquisitionSystems Closed-LoopServo-Control PC Peripherals PortableInstrumentation ProgrammableAttenuation3 DescriptionThe DAC8551is a small,low-power,voltageoutput,16-bitdigi tal-to-analogconverter(DAC).

2 It ismonotonic,providesgoodlinearity, versatile3-wireserialinterfacethatoperat esat clockratesto 30 MHzand is compatiblewith standardSPI , QSPI , Microwire , and digitalsignalprocessor(DSP) DAC8551requiresan externalreferencevoltageto set its DAC8551incorporatesapower-on-resetcircui tthat ensuresthe DACoutputpowersup at 0 V and remainsthereuntil a validwritetakesplaceto the DAC8551containsapower-downfeature,access edovertheserialinterface,that reducesthe currentconsumptionof thedeviceto 200 nA at 5 low-powerconsumptionof this devicein normaloperationmakesit ideallysuitedfor portable, powerconsumptionis V, reducingto lessthan1 W inpower additionalflexibilty,see the DAC8550(SLAS476),a 2's complement-inputcounterpartto the (1)PARTNUMBERPACKAGEBODYSIZE(NOM) DAC8551 VSSOP(8) (1) For all availablepackages,see the orderableaddendumatthe end of the APRIL2005 : DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporatedTableof Contents1 Pin Configurationand Applicationand Deviceand Mechanical,Packaging,and RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (February2017)to RevisionEPage Changedthe VILTestConditionsFrom:VDD= 5 V To: 3 V VDD V and From:VDD= 3 V To: V VDD< 3 Vin Changedthe VIHTestConditionsFrom:VDD= 5 V To: 3 V VDD V and From:VDD= 3 V To.

3 V VDD< 3 Vin (March2016)to RevisionDPage RelativeaccuracyDAC8551,Deletedthe TYPvalueof 3, Changedthe MAXvalueFrom: 8 To: 12 in RelativeaccuracyDAC8551A,Deletedthe TYPvalueof 3, Changedthe MAXvalueFrom: 8 To: 16 in ChangedDifferentialnonlinearityTestCondi tionsFrom:16-bitmonotonicTo: threeseparateentriesin ChangedInputLOWvoltage5 V To: X VDDin ChangedInputLOWvoltage3 V To: X VDDin ChangedInputHIGH voltage5 V MIN VDDin ChangedInputHIGH voltage3 V MIN VDDin (October2006)to RevisionCPage AddedESDR atingstable,FeatureDescriptionsection,De viceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecomme ndationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanica l,Packaging,and APRIL2005 REVISEDJUNE2017 ProductFolderLinks: DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporated5 Pin Configurationand FunctionsDGKP ackage8-PinVSSOPTop ViewPin clockedinto the 24-bitinputshift registeron eachfallingedgeof the all circuitryon the be transferredat ratesup to (activeLOW).

4 This is the framesynchronizationsignalfor the ,it enablesthe inputshift registerand datais transferredin on the fallingedgesof the DACis updatedfollowingthe 24thclock(unlessSYNCis takenHIGH beforethis edge,in whichcasethe risingedgeof SYNC acts as an interruptand the writesequenceis ignoredby the DAC8551 ). , V to VVFB3 IFeedbackconnectionfor the voltageoutputoperation,tie to outputamplifierhas APRIL2005 : DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporated(1)Stre ssesbeyondthoselistedunderAbsoluteMaximu mRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions.

5 Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay (1)MINMAXUNITI nputvoltageGND + + 40105 C CJunctiontemperature,TJ150 C CStoragetemperature,Tstg 65150 C(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.(2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (ESD)ElectrostaticdischargeHuman-bodymod el(HBM),per ANSI/ESDA/JEDECJS-001(1) 2000 VCharged-devicemodel(CDM),per JEDEC specificationJESD22-C101(2) (unlessotherwisenoted)MINNOMMAXUNITS upplyvoltage(VDDto GND) (DIN, SCLK,and SYNC)0 VDDVVREFR eferenceinputvoltage0 VDDVVFBO utputamplifierfeedbackinputVOUTVTAO peratingambienttemperature 40105 C(1)For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC (1) DAC8551 UNITDGK(VSSOP)8 PINSR JAJunction-to-ambientthermalresistance20 6 C/WR JC(top)Junction-to-case(top)thermalresis tance44 C/WR C/W C/W APRIL2005 REVISEDJUNE2017 ProductFolderLinks.

6 DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporated(1)Line aritycalculatedusinga reducedcodesrangeof 485 and 64741at VREF= 5V, codes970 and 63947at VREF= ;outputunloaded,100mVheadroombetweenrefe renceand supply(2)Specifiedby designand characterization;not V to V and 40 C to 105 C (unlessotherwisenoted)PARAMETERTESTCONDI TIONSMINTYPMAXUNITSTATICPERFORMANCE(1)Re solution16 BitsRelativeaccuracyMeasuredby line passingthroughcodes485 and 64741at VREF= 5V, codes970 and 63947atVREF= VDAC8551 12 LSBDAC8551A V VREF V, 0 C TA 105 C V < VREF V, -40 C TA 105 C V VREF V, -40 C TA 0 C 2 LSBZero-codeerrorMeasuredby line passingthroughcodes485 and 64741 2 12mVFull-scaleerror line passingthroughcodes485 and 64741 DAC8551 5 V/ CGaintemperaturecoefficient 1ppmofFSR/ CPSRRP ower-supplyrejectionratioRL= 2 k , CL= 200 (2)

7 Outputvoltagerange0 VREFVO utputvoltagesettlingtimeTo ,0200hto FD00h,RL= 2 k ,0 pF < CL< 200 pF810 sRL= 2 k , CL= 50 pF12 sCapacitiveload stabilityRL= 470pFRL= 2 k 1000pFCodechangeglitchimpulse1 LSB k seriesresistanceon outputimpedanceAt mid-codeinput1 Short-circuitcurrentVDD= 5 V50mAVDD= 3 V20 Power-uptimeComingout of power-downmode,VDD= 5 sComingout of power-downmode,VDD= 3 V5AC PERFORMANCESNRS ignal-to-noiseratioBW = 20 kHz,VDD= 5 V, fOUT= 1 kHz,1st 19 harmonicsremovedfor SNRcalculation95dBTHDT otalharmonicdistortionBW = 20 kHz,VDD= 5 V, fOUT= 1 kHz,1st 19 harmonicsremovedfor SNRcalculation 85dBSFDRS purious-freedynamicrangeBW = 20 kHz,VDD= 5 V, fOUT= 1 kHz,1st 19 harmonicsremovedfor SNRcalculation87dBSINADS ignalto noiseand distortionBW = 20 kHz,VDD= 5 V, fOUT= 1 kHz,1st 19 harmonicsremovedfor SNRcalculation84dBREFERENCEINPUTR eferencecurrentVREF= VDD= 5 V4075 AVREF= VDD= V3045 AReferenceinputrange0 VDDVR eferenceinputimpedance125k 6 DAC8551 SLAS429E APRIL2005.

8 DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporatedElectri calCharacteristics(continued)VDD= V to V and 40 C to 105 C (unlessotherwisenoted)PARAMETERTESTCONDI TIONSMINTYPMAXUNITLOGICINPUTS(2)Inputcur rent 1 AVILI nputLOWvoltage3 V VDD X V VDD< 3 X VDDVIHI nputHIGH voltage3 V VDD X V VDD< 3 X VDDPin ,inputcode= 32768,no load,doesnot includereferencecurrentVDD= V to V,VIH= VDDandVIL= GND160250 AVDD= V to V,VIH= VDDandVIL= GND140240 All power-downmodes,VIH= VDDand VIL= GNDVDD= V to AVDD= V to 2 mA, VDD= 5 V89%Specifiedperformancetemperature 40105 APRIL2005 REVISEDJUNE2017 ProductFolderLinks: DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporated(1)All inputsignalsare specifiedwith tR= tF= 5 ns (10%to 90%of VDD) and timedfroma voltagelevelof (VIL+ VIH) / 2.

9 (2)See Figure1.(3)MaximumSCLK frequencyis 30 MHzat VDD= V to V and 20 MHzat VDD= V to V to V, all specifications 40 C to 105 C (unlessotherwisenoted)(1)(2)PARAMETERTES TCONDITIONSMINTYPMAXUNITt1(3)SCLK cycletimeVDD= V to V50nsVDD= V to V33t2 SCLKHIGH timeVDD= V to V13nsVDD= V to V13t3 SCLKLOW timeVDD= V to V to V13t4 SYNCto SCLK risingedgesetuptimeVDD= V to V0nsVDD= V to V0t5 DatasetuptimeVDD= V to V5nsVDD= V to V5t6 Datahold timeVDD= V to V to SYNC risingedgeVDD= V to V0nsVDD= V to V0t8 MinimumSYNCHIGH timeVDD= V to V50nsVDD= V to V33t924thSCLK fallingedgeto SYNC fallingedgeVDD= V to V100nsFigure1. SerialWriteOperation65432100102468I(mA)( SOURCE/SINK)VOUT(mV)DAC Loaded with FFFFhDAC Loaded with 0000hV= V-10mV0-5-10-4012004080 Temperature ( C)Error (mV)V= 5 VDDV= ( C) Error (mV)V= 5 VDDV= (LSB)0819216384 24576 32768 Digital Input Code40960 4915257344 (LSB)V= 5V, V= (LSB)0819216384 24576 32768 Digital Input Code40960 4915257344 (LSB)V= 5V, V= (LSB)0819216384 24576 32768 Digital Input Code40960 4915257344 (LSB)V= 5V, V= APRIL2005 : DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017, 5 VAt TA= 25 C (unlessotherwisenoted)Figure2.

10 LinearityErrorand DifferentialLinearityErrorvsDigitalInput Code( 40 C)Figure3. LinearityErrorand DifferentialLinearityErrorvsDigitalInput CodeFigure4. LinearityErrorand DifferentialLinearityErrorvsDigitalInput Code(105 C)Figure5. Zero-ScaleErrorvs TemperatureFigure6. Full-ScaleErrorvs TemperatureFigure7. Sourceand SinkCurrentCapability1800160014001200100 08006004002000012345V(V)LOGICIDD(mA)TA= 25 C, SCL Input (all other inputs = GND)VDDREF= V= (2 s/div)mV= 5VV= Code: D000To Code: FFFFDDREFT rigger Pulse 5V/divZoomed Rising Edge1mV/divRising Edge1 (V)DDIDD(mA)VREFDD= VReference Current Included, No (V)DDPower-Down Current (mA)VREFDD= V30025020015010050008192245764096057344 65536163843276849152 Digital Input CodeIDD(mA)VDDREF= V= 5 VReference Current Included250200150100500I( A)mDDV= V= 5 VREFDD-40-10110205080 Temperature ( C) APRIL2005 REVISEDJUNE2017 ProductFolderLinks: DAC8551 SubmitDocumentationFeedbackCopyright 2005 2017,TexasInstrumentsIncorporatedVDD= 5 V (continued)At TA= 25 C (unlessotherwisenoted)Figure8.