DATA SHEET - UdG

1 data SHEETP roduct specificationFile under Integrated Circuits, IC171999 Apr 12 INTEGRATED CIRCUITSPCD854448 84 pixels matrix LCDcontroller/driver1999 Apr 122 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD8544 CONTENTS1 FEATURES2 GENERAL DESCRIPTION3 APPLICATIONS4 ORDERING INFORMATION5 BLOCK to R47 row driver to C83 column driver ,VSS2: negative power supply ,VDD2: positive power supply ,VLCD2: LCD power , T2, T3 and T4: test : serial data : serial clock : mode : chip : : reset7 FUNCTIONAL Counter (AC) data RAM (DDRAM) address row and column D and Y address of X address of VOP value9 LIMITING VALUES10 HANDLING11DC CHARACTERISTICS12AC INFORMATION14 BONDING PAD pad pad location15 TRAY INFORMATION16 DEFINITIONS17 LIFE SUPPORT APPLICATIONS1999 Apr 123 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD85441 FEATURES Single chip LCD controller/driver 48 row, 84 column outputs Display data RAM 48 84 bits On-chip: Generation of LCD supply voltage (external supplyalso possible) Generation of intermediate LCD bias voltages Oscillator requires no external components (externalclock also possible).

2 ExternalRES (reset) input pin Serial interface maximum Mbits/s CMOS compatible inputs Mux rate: 48 Logic supply voltage range VDDto VSS: to V Display supply voltage range VLCDto VSS to V with LCD voltage internally generated(voltage generator enabled) to V with LCD voltage externally supplied(voltage generator switched-off). Low power consumption, suitable for battery operatedsystems Temperature compensation of VLCD Temperature range: 25 to +70 DESCRIPTIONThe PCD8544 is a low power CMOS LCD controller/driver,designed to drive a graphic display of 48 rows and84 columns. All necessary functions for the display areprovided in a single chip, including on-chip generation ofLCD supply and bias voltages, resulting in a minimum ofexternal components and low power PCD8544 interfaces to microcontrollers through aserial bus PCD8544 is manufactured in n-well Telecommunications INFORMATIONTYPE NUMBERPACKAGENAMEDESCRIPTIONVERSIONPCD85 44U chip with bumps in tray.

3 168 bonding pads + 4 dummy pads 1999 Apr 124 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD85445 BLOCK Block , full pagewidthMGL629 COLUMN DRIVERSDATA LATCHESDISPLAY data RAM(DDRAM)48 84 ADDRESS COUNTERDATAREGISTERROW DRIVERSSHIFT REGISTERRESETTIMINGGENERATORDISPLAYADDRE SSCOUNTEROSCILLATORI/O BUFFERBIASVOLTAGEGENERATORVLCDGENERATORV LCD2 VLCD1 VDD1 to VDD2 VSS1 to VSS2T2T1T3T4 SCLKSDINSCED/CRESOSCC1 to C83R0 to R47 PCD85441999 Apr 125 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD85446 PINNINGNote1. For further details, see and Table DRIVER OUTPUTST hese pads output the row DRIVER OUTPUTST hese pads output the column ,VSS2:NEGATIVE POWER SUPPLY RAILSS upply rails VSS1 and VSS2 must be connected ,VDD2:POSITIVE POWER SUPPLY RAILSS upply rails VDD1 and VDD2 must be connected to R47 LCD row driver outputsC0 to C83 LCD column driver outputsVSS1,VSS2groundVDD1,VDD2supply voltageVLCD1,VLCD2 LCD supply voltageT1test 1 inputT2test 2 outputT3test 3 input/outputT4test 4 inputSDIN serial data inputSCLK serial clock inputD/Cdata/commandSCEchip enableOSCoscillatorRESexternal reset inputdummy1, 2, 3, 4 not ,VLCD2: LCDPOWER SUPPLYP ositive power supply for the liquid crystal display.

4 Supplyrails VLCD1 and VLCD2 must be connected , T2, T3 ANDT4:TEST PADST1, T3 and T4 must be connected to VSS, T2 is to be leftopen. Not accessible to :SERIAL data LINEI nput for the data :SERIAL CLOCK LINEI nput for the clock signal: to :MODE SELECTI nput to select either command/address or data :CHIP ENABLEThe enable pin allows data to be clocked in. The signal isactive :OSCILLATORWhen the on-chip oscillator is used, this input must beconnected to VDD. An external clock signal, if used, isconnected to this input. If the oscillator and external clockare both inhibited by connecting the OSC pin to VSS, thedisplay is not clocked and may be left in a DC avoid this, the chip should always be put intoPower-down mode before stopping the :RESETThis signal will reset the device and must be applied toproperly initialize the chip. The signal is active Apr 126 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD85447 FUNCTIONAL on-chip oscillator provides the clock signal for thedisplay system.

5 No external components are required andthe OSC input must be connected to VDD. An externalclock signal, if used, is connected to this Counter (AC)The address counter assigns addresses to the displaydata RAM for writing. The X-address X6to X0 and theY-address Y2to Y0 are set separately. After a writeoperation, the address counter is automaticallyincremented by 1, according to the V data RAM (DDRAM)The DDRAM is a 48 84 bit static RAM which stores thedisplay data . The RAM is divided into six banks of 84 bytes(6 8 84 bits). During RAM access, data is transferredto the RAM through the serial interface. There is a directcorrespondence between the X-address and the columnoutput generatorThe timing generator produces the various signalsrequired to drive the internal circuits. Internal chipoperation is not affected by operations on the data address counterThe display is generated by continuously shifting rows ofRAM data to the dot matrix LCD through the columnoutputs.

6 The display status (all dots on/off andnormal/inverse video) is set by bits E and D in the displaycontrol row and column driversThe PCD8544 contains 48 row and 84 column drivers,which connect the appropriate LCD bias voltages insequence to the display in accordance with the data to bedisplayed. Figure 2 shows typical waveforms. Unusedoutputs should be left Apr 127 Philips SemiconductorsProduct specification48 84 pixels matrix LCD Typical LCD driver (t) = C1(t) - R0(t).Vstate2(t) = C1(t) - R1(t).MGL637 ROW 0R0 (t)ROW 1R1 (t)COL 0C0 (t)COL 1C1 (t)VLCDV2V3V4V5 VSSVLCDVSSVLCDVSSVLCDVLCDV3 - VSSVLCD - V2V3 - V20 VVLCDV3 - VSSVLCD - V2V3 - V20 V VLCDV4 - VLCDVSS - V5V4 - V50 V VLCDV4 - VLCDVSS - V5V4 - V50 VVSSV2V3V4V5V2V3V4V5V2V3V4V5frame nframe n + 47 Vstate1(t)Vstate2(t)Vstate1(t)Vstate2(t) 1999 Apr 128 Philips SemiconductorsProduct specification48 84 pixels matrix LCD DDRAM to display of LCDMGL636 DDRAM bank 0R0R8R16R24R32R40R47bank 1bank 2bank 3bank 4bank 5 LCD1999 Apr 129 Philips SemiconductorsProduct specification48 84 pixels matrix LCD is downloaded in bytes into the 48 by 84 bits RAMdata display matrix of PCD8544, as indicated inFigs.

7 3, 4, 5 and 6. The columns are addressed by theaddress pointer. The address ranges are: X 0 to 83(1010011), Y 0 to 5 (101). Addresses outside theseranges are not allowed. In the vertical addressing mode(V = 1), the Y address increments after each byte ( ). After the last Y address (Y = 5), Y wraps aroundto 0 and X increments to address the next column. In thehorizontal addressing mode (V = 0), the X addressincrements after each byte (see ). After the lastX address (X = 83), X wraps around to 0 andY increments to address the next row. After the very lastaddress (X = 83 and Y = 5), the address pointers wraparound to address (X=0andY=0). RAM format, , full Sequence of writing data bytes into RAM with vertical addressing (V = 1).handbook, halfpageMGL63900550354321076Y-addressX-a ddress831999 Apr 1210 Philips SemiconductorsProduct specification48 84 pixels matrix LCD Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

8 Handbook, compensationDue to the temperature dependency of the liquid crystals viscosity, the LCD controlling voltage VLCD must beincreased at lower temperatures to maintain optimumcontrast. Figure 7 shows VLCD for high multiplex the PCD8544, the temperature coefficient of VLCD, canbe selected from four values (see Table 2) by setting bitsTC1and VLCD as function of liquid crystal temperature (typical values).handbook, halfpageMGL6410 C(1)(2)(3)(4)VLCD temperature(1) Upper limit.(2) Typical curve.(3) Temperature coefficient of IC.(4) Lower Apr 1211 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD85448 INSTRUCTIONSThe instruction format is divided into two modes: If D/C(mode select) is set LOW, the current byte is interpreted ascommand byte (see Table 1). Figure 8 shows an exampleof a serial data stream for initializing the chip.

9 If D/C is setHIGH, the following bytes are stored in the display dataRAM. After every data byte, the address counter isincremented level of the D/C signal is read during the last bit of instruction can be sent in any order to the MSB of a byte is transmitted first. Figure 9 shows onepossible command stream, used to set up the LCD serial interface is initialized whenSCE is HIGH. In thisstate, SCLK clock pulses have no effect and no power isconsumed by the serial interface. A negative edge onSCEenables the serial interface and indicates the start of a General format of data , halfpageMGL666datadataMSB (DB7)LSB (DB0) Serial data stream, , full pagewidthMGL642function set (H = 1)bias systemset VOPtemperature controlfunction set (H = 0)display controlX addressY addressFigures 10 and 11 show the serial bus protocol. WhenSCE is HIGH, SCLK clock signals are ignored;during the HIGH time ofSCE, the serial interface isinitialized (see ) SDIN is sampled at the positive edge of SCLK D/C indicates whether the byte is a command (D/C=0)or RAM data (D/C = 1); it is read with the eighth SCLK pulse IfSCE stays LOW after the last bit of a command/databyte, the serial interface expects bit 7 of the next byte atthe next positive edge of SCLK (see ) A reset pulse withRES interrupts the data is written into the RAM.

10 The registers arecleared. IfSCE is LOW after the positive edge ofRES,the serial interface is ready to receive bit 7 of acommand/ data byte (see ).1999 Apr 1212 Philips SemiconductorsProduct specification48 84 pixels matrix LCD Serial bus protocol - transmission of one , full pagewidthDB7 Serial bus protocol - transmission of several , full pagewidthDB7 SDINSCLKSCED/CDB6 DB5 DB4 DB3DB0DB1DB2DB7 DB6 DB5DB0 DB7 DB6 DB5 MGL631DB4 DB3 DB2 DB11999 Apr 1213 Philips SemiconductorsProduct specification48 84 pixels matrix LCD Serial bus reset function (SCE).handbook, full pagewidthDB7 SDINSCLKRESSCED/CDB6 DB5 DB4 DB3DB0DB1DB2DB7 DB6 DB5DB0 DB7 DB6 DB5 MGL632DB4 DB3 DB2 Serial bus reset function (RES).handbook, full pagewidthDB7 SDINSCLKRESSCED/CDB6 DB5 DB4 DB3DB7 DB6 DB5 DB4DB7 DB6 DB5 DB4 MGL633DB3 DB2 DB1 DB01999 Apr 1214 Philips SemiconductorsProduct specification48 84 pixels matrix LCD controller/driverPCD8544 Table 1 Instruction setTable 2 Explanations of symbols in Table 1 INSTRUCTIOND/C COMMAND BYTEDESCRIPTIONDB7DB6DB5DB4DB3DB2DB1DB0( H = 0 or 1)NOP0 00000000no operationFunction set000100 PDVH power down control; entrymode; extended instruction setcontrol (H)Write data1D7D6D5D4D3D2D1D0writes data to display RAM(H = 0)Reserved0000001 XXdo not useDisplay control000001D0 Esets display configurationReserved00001 XXXXdo not useSet Y address ofRAM0 01000Y2Y1Y0sets Y-address of RAM;0 Y 5 Set X address ofRAM01X6X5X4X3X2X1X0sets X-address part of RAM.