Design Review Checklist - SUWITO

1 HAUW SUWITO , CONSULTANT Design Review Checklist Table of Content Checklist for Design Kick-off Checklist for RTL code release Design Checklist for Mask Release Design Introduction This Checklist consists of three parts, each for a specific Design milestone: (1) Design Kick-off (2) RTL Release and (3) Tapeout. Design Kick-off starts the Design activity. The team reviews and agrees upon the project plan, Design specification and other project documents before starting the Design work. The RTL Release milestone may consist of several releases, depending on the scope of the project. A RTL of major block or the entire chip is released after simulations, synthesis and timing closure have been completed. Tapeout milestone starts the mask production after all physical, timing and functional are reviewed and signed off. 1000 Bristol North Suite#17-222, Newport Beach, Tel: Fax: Checklist for Design Kick-off Review Item Activity/Deliverable Complete Punch-List1 Notes/Issues 1.

2 Project name 2. Design requirement acceptance by engineering 3. Customer feedbacks included in the requirement list. 4. Design specification signed-off by all parties 5. Production test requirements (Self-tests, scan, maximum test time, maximum tester capacity) 6. Special requirement for chip production (process ID) 7. Product cost estimate (die size, package cost, test time, yield) 8. Chip packaging specification (custom tooling vs. open tooling, pad sequence, special physical Design requirements) 9. Architecture and chip partitioning definition 10. Clock domain list 11. Major busses analysis completed 12. Process technology requirements 13. Target library and revision List of cells to be excluded from library (set_don t_use) 14. Target I/O library and revision 15. Special I/O requirement 16.

3 Complete analog IP list and availability 17. Complete list of embedded memory and availability 18. Complete list of digital IP and availability 19. Simulation plan completed (system, functional block, functional top, gate-level block, gate-level top) 20. Validation plan completed (PCB, test equipment, list of tests) 21. Project timeline signed-off 22. Resource plan signed-off (including external) 23. Project cost budget approved 24. Project risk assessment approved 1 Itemized list documenting incomplete items. 1000 Bristol North Suite#17-222, Newport Beach, Tel: Fax: Page 2 of 5 Checklist for RTL code release Design Review Item Activity/Deliverable Complete Punch-List2 Notes/Issues 1. Project name 2. Any changes on Design specification signed-off by all parties 3.

4 Any changes to product cost estimate (die size, package cost, test time, yield) 4. Any changes to chip packaging specification (custom tooling vs. open tooling, pad sequence, special physical Design requirements) 5. Any changes to architecture and chip partitioning definition (including bus architecture) 6. Clock domain list updated 7. Simulation plan updated 8. Block functional simulation completed 9. Top level functional simulation completed 10. Logic and functional Design Review completed 11. Synthesis script Review , especially the setup file 12. Logic synthesis report reviewed 13. Test synthesis report reviewed 14. SDF available (identify source) 15. Static timing analysis Review (slow) Clock-Clock & I/O 16. Clock skew report 17. Block gate level simulation completed 18. Top level gate level simulation completed 19.

5 ATPG simulation 20. Revision control database checked 21. List of violations, open issues and risk assessment 2 Itemized list documenting incomplete items. 1000 Bristol North Suite#17-222, Newport Beach, Tel: Fax: Page 3 of 5 Checklist for Mask Release Design Review Item Activity/Deliverable Complete Punch-List3 Notes/Issues 1. Project name 2. Any changes on Design specification signed-off by all parties 3. Any changes to product cost estimate (die size, package cost, test time, yield) 4. Any changes to chip packaging specification (custom tooling vs. open tooling, pad sequence, special physical Design requirements) 5. Any changes to architecture and chip partitioning definition (including bus architecture) 6. Clock domain list updated 7.

6 Simulation plan updated 8. Top level functional regression report reviewed 9. Final SDF from extraction 10. Static timing analysis Review Clock-Clock & I/O Slow and fast cases Mission and test modes 11. Top-level gate level regression completed (slow) 12. ATPG pattern (fast) 13. JTAG simulation 14. ECO verified (formal verification) 15. Analog cells simulation Review 16. Analog cells layout Review 17. High-fanout, high capacitive nets Review 18. Power stripe Review , chip power dissipation 19. Electromigration Review (power bussing, clock, reset) 20. Bond diagram Review 21. Packaging & substrate Review 22. High-speed I/O simulation Review 23. I/O ground bounce Review 24. Spare gates Review 25. ESD structure Review 26. Antenna violation report 27. Metal ratio violation report 28.

7 DRC rule deck and report Review 29. LVS report Review 30. Validation plan Review 31. Validation readiness Review 32. Software driver readiness Review 3 Itemized list documenting incomplete items. 1000 Bristol North Suite#17-222, Newport Beach, Tel: Fax: Page 4 of 5 Item Activity/Deliverable Complete Punch-List3 Notes/Issues 33. Foundry documentations ready 34. Revision control database checked 35. List of violations, open issues and risk assessment 1000 Bristol North Suite#17-222, Newport Beach, Tel: Fax: Page 5 of 5