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Digital Phase Locked Loop - University of Maine
3.1.2 2 Input NAND Figure 3 shows a common 2 input CMOS nand gate. A 2:1 overall well width ratio (see Inverter) was employed. 3.1.3 3 Input NAND Figure 4 shows a common 3 input CMOS nand gate. A 2:1 overall well width ratio (see Inverter) was employed. 3.1.4 8 Input NAND Figure 5 shows a common 8 input CMOS nand gate.
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ECE 547 - UNIVERSITY OF MAINE 1 8-Bit Arithmetic Logic Unit
ece.umaine.eduA random input stream similar to the one shown in Figure 5 was applied to each input of the ALU. The current through the voltage supply pin for a 10 MHZ random input stream is shown in Figure 6. The average current for this case is 2.18 mA (8.51 mA RMS). Figure 7 shows the current through the voltage supply pin for a 50 MHZ random input stream.
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