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DM50x SoC for Vision Analytics 15mm Package (ABF) Silicon ...

ProductFolderOrderNowTechnicalDocumentsT ools &SoftwareSupport &CommunityAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand NOVEMBER2016 REVISEDMAY2018DM505 SoC for VisionAnalytics15mmPackage(ABF) ArchitectureDesignedfor VisionAnalyticsApplications Videoand ImageProcessingSupport Full-HDVideo(1920 1080p,60 fps) VideoInputand VideoOutput Up to 2 C66xFloating-PointVLIWDSP FullyObject-CodeCompatibleWithC67xandC64 x+ Up to Thirty-two16 16-BitFixed-PointMultipliesper Cycle Up to 512kBof On-ChipL3 RAM Level3 (L3) and Level4 (L4) Interconnects MemoryInterface(EMIF)Module SupportsDDR3/DDR3 Lup to DDR-1066 SupportsDDR2up to DDR-800 SupportsLPDDR

Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

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Transcription of DM50x SoC for Vision Analytics 15mm Package (ABF) Silicon ...

1 ProductFolderOrderNowTechnicalDocumentsT ools &SoftwareSupport &CommunityAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand NOVEMBER2016 REVISEDMAY2018DM505 SoC for VisionAnalytics15mmPackage(ABF) ArchitectureDesignedfor VisionAnalyticsApplications Videoand ImageProcessingSupport Full-HDVideo(1920 1080p,60 fps) VideoInputand VideoOutput Up to 2 C66xFloating-PointVLIWDSP FullyObject-CodeCompatibleWithC67xandC64 x+ Up to Thirty-two16 16-BitFixed-PointMultipliesper Cycle Up to 512kBof On-ChipL3 RAM Level3 (L3) and Level4 (L4) Interconnects MemoryInterface(EMIF)Module SupportsDDR3/DDR3 Lup to DDR-1066 SupportsDDR2up to DDR-800 SupportsLPDDR2up to DDR-667 Up to 2 GBSupported DualArm Cortex -M4 ImageProcessor(IPU) VisionAccelerationPac EmbeddedVisionEngine(EVE)

2 DisplaySubsystem DisplayControllerWithDMAE ngine CVIDEO/ SD-DACTV AnalogCompositeOutput VideoInputPort (VIP)Module Supportfor up to 4 MultiplexedInputPorts On-chipTemperatureSensorThatis CapableofGeneratingTemperatureAlerts General-PurposeMemoryController(GPMC) EnhancedDirectMemoryAccess(EDMA)Controll er 3-Port(2 External)GigabitEthernet(GMAC)Switch ControllerAreaNetwork(DCAN)Module ModularControllerAreaNetwork(MCAN)Module Eight32-BitGeneral-PurposeTimers ThreeConfigurableUARTM odules FourMultichannelSerialPeripheralInterfac es(McSPI) QuadSPI Interface Two Inter-IntegratedCircuit(I2C) Ports ThreeMultichannelAudioSerialPorts(McASP) Modules MultiMediaCard/SecureDigital/SecureDigit alInputOutputInterface(MMC/SD/SDIO) Up to 126 General-PurposeI/O (GPIO)Pins Power,Reset,and ClockManagement On-ChipDebugWithCToolsTechnology AutomotiveAEC-Q100 Qualified 15 15mm, ,367-PinPBGA(ABF)

3 8-Channel10-bitADC MIPICSI-2 CameraSerialInterface PWMSS Full HW ImagePipe:DPC,CFA,3D-NF,RGB-YUV WDR,HW LDCand Perspective2DM505 SPRS976E NOVEMBER2016 2016 2018, Drones Robotics IndustrialTransportation(Forklift,Rail,A griculture) Factoryand DM505is a highlyoptimizeddevicefor VisionAnalyticsand MachineVisionprocessingin Industrialproductssuchas drones,robots,forklifts,railroadand optimalmix of real time performance,low power,smallformfactorand cameraprocessingfor systemsto interactin moreintelligent,usefulwayswith thephysicalworldand the peoplein DM505incorporatesa heterogeneous,scalablearchitecturethat includesa mix of TI s fixedandfloating-pointTMS320C66xdigitals ignalprocessor(DSP)generationcores,Visio nAccelerationPac(EVE)

4 , powerdesignsto meetdemandingembeddedsystembudgetswithou tsacrificingreal-timeprocessingperforman ceto DM505also integratesa host of peripheralsincludinginterfacesfor multi-camerainput(bothparalleland serial),displayoutputs,audioand serialI/O, CANand providesapplicationspecifichardwareandso ftwarethroughour DesignNetworkPartnersandacompleteset of developmenttoolsfor the Arm,andDSP,includingC compilerswithTI RTOS toacceleratetime to (367) ControllersGPMC 8b/16bwith up to 16b ECCLPDDR2 / DDR2/DDR3 / DDR3L32b with 8b ECCT imer x8 Mailbox/Spinlock10-bit ADCC ontrol ModuleEDMAGPIO x4 PWMSSx1 MMUx1 PRCMS ystemI2C x2 SPI x4 QSPI x1 SDIO x1 DCAN with ECCUART x3 McASP x3 Serial InterfacesGMACC onnectivityEDMA 2 TCL2256 KBCacheC66xL1D 32 KBL1P 32 KBDSP Subsystem x2 Video Input PortCALLVDSRXCSI2 ISPV ideo Front Endup to 512KB RAMwith ECCIPU with ECCDual Cortex M432KB ROMEVE 16 MACEDMA 2 TCVisionAcceleratorOSDR esizingCSCSD-DACDVOUTD

5 IsplaySubsystemInterconnectDM505 Copyright 2016, Texas Instruments IncorporatedMCAN(CAN-FD)with NOVEMBER2016 REVISEDMAY2018 SubmitDocumentationFeedbackDeviceOvervie wCopyright 2016 2018, is functionalblockdiagramof the DM505 BlockDiagram4DM505 SPRS976E NOVEMBER2016 ContentsCopyright 2016 2018,TexasInstrumentsIncorporatedTableof Contents1 TerminalConfigurationand Hour(POH) Applications,Implementation,and Deviceand NOVEMBER2016 REVISEDMAY2018 SubmitDocumentationFeedbackRevisionHisto ryCopyright 2016 2018,TexasInstrumentsIncorporated2 RevisionHistoryChangesfromJuly31, 2017to May5, 2018(fromD Revision(July2017)to E Revision)

6 Page Updated ARM referencesto Arm in , Updated ARM referencesto Arm in Table3-1, Addedclarificationnotesto ,Pin UpdatedI/O VOLTAGEVALUE columnin Table4-1,Pin Attributesto all ddr RemovedMUX16optionin Table4-1,Pin UpdatedsomeGPMC ball resetreleasemuxmodevaluesin Table4-1,Pin RemovedballsfromTable4-16, Updated ARM referencesto Arm in Table4-26, Addedmissingballsin Table4-29, Addedrecommendedand absolutemaximumvoltagevaluesfor vdds_ddr*powerpins whenLPDDR2andDDR2are UpdatedTable5-5, Removedvoltagehigh levellimitsfromTable5-11,LVCMOSCSI2DC Addedreferencesto notesunderTable5-11,LVCMOSCSI2DC ,TimingParametersand UpdatedDPLLCLKOUT outputfrequencyin Table5-26, UpdatedMcSPIand UpdatedPhasepolarityin all Addedqspi1_cs1to all QSPIIOSETsin Table5-51, AddedTable5-59.

7 AddedCANdelaytime receiveand transmitparametersin relationto the shift Updated"ARM" referencesto "Arm" Table5-82,SwitchingCharacteristicsOverRe commendedOperatingConditionsfor Updated ARM referencesto Arm in Section6, ,Lossof Addednew parameterin Table7-11,LengthMismatchGuidelinesfor CSI-2( Gbps)..237 Updated ARM referencesto Arm in the NOVEMBER2016 2016 2018,TexasInstrumentsIncorporated3 showsa comparisonbetweendevices,highlightingthe DeviceComparisonFeaturesDeviceDM505 MDM505 LFeaturesCTRL_WKUP_STD_FUSE_DIE_ID_2[31. ]

8 24]BasePN registerbitfieldvalue(3)156 (0x9C65)156 (0x9C5D)Processors/AcceleratorsSpeedGrad esRRC66x VLIWDSPDSP1 YesYesDSP2 YesNoDisplaySubsystemVOUT1 YesYesSD_DACYesYesEmbeddedVisionEngine(E VE)EVE1 YesYesArm DualCortex-M4 ImageProcessingUnit (IPU)IPU1 YesYesImagingSubsystemProcessor(ISS)with MIPICSI-2and CPI portsISPYesYesWDR& MeshLDC(1)YesYesCAL_AYesYesCAL_BYesYesLV DS-RXYesYesCPIYesYesVideoInputPort(VIP)V IP1vin1aYesYesvin1bYesYesvin2aYesYesvin2 bYesYesProgram/DataStorageOn-ChipSharedM emory(RAM)OCMC_RAM1512kB256kBGeneral-Pur poseMemoryController(GPMC)GPMCYesYesLPDD R2/DDR2/DDR3/DDR3 LMemoryControllerEMIF1(optionalwithSECDE D)up to 2 GBup to 2 GBPeripheralsControllerAreaNetworkInterf ace(CAN)DCAN1 YesYesMCANYes(2)Yes(2)EnhancedDMA(EDMA)E DMAYesYesEmbedded8 channelADCADCYesYesEthernetSubsystem(Eth ernetSS)GMAC_SW[0]RGMIIOnlyRGMIIOnlyGMAC _SW[1]RGMIIOnlyRGMIIOnlyGeneral-PurposeI O (GPIO)GPIOUp to 126Up to 126 Inter-IntegratedCircuitInterface(I2C)

9 I2C22 SystemMailboxModuleMAILBOX22 MultichannelAudioSerialPort (McASP)McASP116 serializers16 serializersMcASP26 serializers6 serializersMcASP36 serializers6 NOVEMBER2016 REVISEDMAY2018 SubmitDocumentationFeedbackDeviceCompari sonCopyright 2016 2018,TexasInstrumentsIncorporatedTable3- 1. DeviceComparison(continued)FeaturesDevic eDM505 MDM505 LMultiMediaCard/SecureDigital/SecureDigi talInputOutputInterface(MMC/SD/SDIO)MMC1 x SDIO4b1x SDIO4bMultichannelSerialPeripheralInterf ace(McSPI)McSPI44 QuadSPI (QSPI)QSPIYesYesSpinlockModuleSPINLOCKYe sYesTimers,General-PurposeTIMER88 Pulse-WidthModulationSubsystem(PWMSS)PWM SS1 YesYesUniversalAsynchronousReceiver/Tran smitter(UART)UART33(1) WideDynamicRangeand LensDistortionCorrection.

10 (2) DevicesupportsFD (FlexibleDataRate)(3) For moredetailsaboutthe CTRL_WKUP_STD_FUSE_DIE_ID_2registerand BasePN bitfield,see NOVEMBER2016 FunctionsCopyright 2016 2018,TexasInstrumentsIncorporated4 TerminalConfigurationand DiagramFigure4-1 showsthe ball locationsfor the 367 plasticball grid array(PBGA)packageand are usedinconjunctionwith Table4-1 throughTable4-27to locatesignalna


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