DM74LS181 4-Bit Arithmetic Logic Unit

1 2000 Fairchild Semiconductor 1988 Revised April 2000DM74LS181 4-Bit Arithmetic Logic UnitDM74LS1814-Bit Arithmetic Logic UnitGeneral DescriptionThe DM74LS181 is a 4-Bit Arithmetic Logic Unit (ALU)which can perform all the possible 16 Logic operations ontwo variables and a variety of Arithmetic 16 Arithmetic operations: add, subtract, com-pare, double, plus twelve other Arithmetic operationsnProvides all 16 Logic operations of two variables: exclusive-OR, compare, AND, NAND, OR, NOR, plusten other Logic operationsnFull lookahead for high speed Arithmetic operation onlong words Ordering Code: Logic SymbolsActive High OperandsActive Low OperandsVCC = Pin 24 GND = Pin 12 Connection DiagramPin DescriptionsOrder NumberPackage NumberPackage DescriptionDM74LS181NN24A24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, WidePin NamesDescriptionA0 A3 Operand Inputs (Active LOW)B0 B3 Operand Inputs (Active LOW)S0 S3 Function Select InputsMMode Control InputCnCarry InputF0 F3 Function Outputs (Active LOW)A = BComparator OutputGCarry Generate Output (Active LOW)PCarry Propagate Output (Active LOW)Cn+4 Carry DescriptionThe DM74LS181 is a 4-Bit high speed parallel ArithmeticLogic Unit (ALU).

2 Controlled by the four Function Selectinputs (S0 S3) and the Mode Control input (M), it can per-form all the 16 possible Logic operations or 16 differentarithmetic operations on active HIGH or active LOW oper-ands. The Function Table lists these operationsWhen the Mode Control input (M) is HIGH, all internal car-ries are inhibited and the device performs Logic operationson the individual bits as listed. When the Mode Controlinput is LOW, the carries are enabled and the device per-forms Arithmetic operations on the two 4-Bit words. Thedevice incorporates full internal carry lookahead and pro-vides for either ripple carry between devices using the Cn+4output, or for carry lookahead between packages using thesignals P (Carry Propagate) and G (Carry Generate). In theADD mode, P indicates that F is 15 or more, while G indi-cates that F is 16 or more. In the SUBTRACT mode, P indi-cates that F is zero or less, while G indicates that F is lessthan zero.

3 P and G are not affected by carry in. Whenspeed requirements are not stringent, it can be used in asimple ripple carry mode by connecting the Carry output(Cn+4) signal to the Carry input (Cn) of the next unit. Forhigh speed operation the device is used in conjunction withthe 9342 or 93S42 carry lookahead circuit. One carry loo-kahead package is required for each group of fourDM74LS181 devices. Carry lookahead can be provided atvarious levels and offers high speed capability overextremely long word A = B output from the device goes HIGH when all fourF outputs are HIGH and can be used to indicate logicequivalence over four bits when the unit is in the subtractmode. The A = B output is open-collector and can be wired-AND with other A = B outputs to give a comparison formore than four bits. The A = B signal can also be used withthe Cn+4 signal to indicate A > B and A < Function Table lists the Arithmetic operations that areperformed without a carry in.

4 An incoming carry adds a oneto each operation. Thus, select code LHHL generates Aminus B minus 1 (2s complement notation) without a carryin and generates A minus B when a carry is subtraction is actually performed by complemen-tary addition (1s complement), a carry out means borrow;thus a carry is generated when there is no underflow andno carry is generated when there is underflow. As indi-cated, this device can be used with either active LOWinputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case thetable lists the operations that are performed to the oper-ands labeled inside the Logic TableNote 1: Each bit is shifted to the next most significant 2: Arithmetic operations expressed in 2s complement SelectActive LOW OperandsActive HIGH OperandsInputs& Fn Outputs& Fn OutputsLogicArithmetic(Note 2)LogicArithmetic(Note 2)S3S2S1S0(M = H)(M = L) (Cn = L)(M = H)(M = L) (Cn = H)LLLLAA minus 1 AALLLHABAB minus 1A + BA + BLLHLA + BAB minus 1A BA + BLLHHL ogic 1minus 1 Logic 0minus 1 LHL LA + BA plus (A + B)ABA plus ABLHLHBAB plus (A + B)B(A + B) plus ABLHHLA BA minus B minus 1A BA minus B minus 1 LHHHA + BA + BABAB minus 1 HLLLA BA plus (A + B)A + BA plus ABHL LHA BA plus BA BA plus BHLHLBAB plus (A + B)B(A + B) plus ABHLHHA + BA + BABAB minus 1 HHLLL ogic 0A plus A (Note 1) Logic 1A plus A (Note 1)HH L HABAB plus AA + B(A + B) plus AHHHLABAB minus AA + B(A + B) plus AHHHHAAAA minus Maximum Ratings(Note 3)Note 3.

5 The Absolute Maximum Ratings are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum Recommended Operating Conditions table will define the conditionsfor actual device Operating ConditionsElectrical Characteristics over recommended operating free air temperature range (unless otherwise noted)Note 4: All typicals are at VCC = 5V, TA = 25 5: Not more than one output should be shorted at a time, and the duration should not exceed one Voltage7 VInput Voltage7 VOperating Free Air Temperature Range0 C to +70 CStorage Temperature Range 65 C to +150 CSymbolParameterMinNomMaxUnitsVCCS upply Level Input Voltage2 VVILLOW Level Input Level Output Current Level Output Current8mATAFree Air Operating Temperature070 CSymbolParameterConditionsMinTypMaxUnits (Note 4)VIInput Clamp VoltageVCC = Min, II = 18 mA Level VCC = Min, IOH = Max, VoltageVIL = MaxVOLLOW Level VCC = Min, IOL = Max, VoltageVIH = MinIOL = 4 mA, VCC = Current @ MaxVCC = Max, VI = 7VM VoltageAn, LevelVCC = Max, VI = input20 Input CurrentAn, Bn60 ASn80Cn100 IILLOW LevelVCC = Max, VI = input CurrentAn, Bn CircuitVCC = Max 20 100mAOutput Current(Note 5)

6 ICCS upply CurrentVCC = Max, Bn, Cn = GND37mASn, M, An = CharacteristicsVCC = 5V, TA = 25 CSum Mode Test Table 1 Function Inputs S0 = S3 = , S1 = S2 = M = 0 VSymbolParameterConditionsCL = 15 pFUnitsMinMaxtPLHP ropagation DelayM = GND27nstPHLCn to Cn+420tPLHP ropagation DelayM = GND26nstPHLCn to F20tPLHP ropagation DelayM, S1, S2 = GND;29nstPHLA or B to G (Sum)S1, S3 = DelayM, S0, S3 = GND;32nstPHLA or B to G (Diff)S1, S2 = DelayM, S1, S2 = GND;30nstPHLA or B to P (Sum)S0, S3 = DelayM, S0, S3 = GND;30nstPHLA or B to P (Diff)S1, S2 = DelayM, S1, S2 = GND;32nstPHLAi or Bi to Fi(Sum)S0, S3 = DelayM, S0, S3 = GND;32nstPHLAi or Bi to Fi(Diff)S1, S2 = DelayM = or B to F ( Logic )29tPLHP ropagation DelayM, S1, S2 = GND;38nstPHLA or B to Cn+4 (Sum)S0, S3 = DelayM, S0, S3 = GND;41nstPHLA or B to Cn+4 (Diff)S1, S2 = DelayM, S0, S3 = GND;50nstPHLA or B to A = BS1, S2 = ;62RL = 2 k to InputOther Data InputsOutputSymbolUnderSame and BtPLHBiAiNoneRemainingCnFitPHLA and BtPLHABNoneNoneRemainingPtPHLA and B, CntPLHBANoneNoneRemainingPtPHLA and B, CntPLHANoneBRemainingRemainingGtPHLBA, CntPLHBNoneARemainingRemainingGtPHLBA, CntPLHANoneBRemainingRemainingCn+4tPHLBA , CntPLHBNoneARemainingRemainingCn+4tPHLBA , CntPLHCnNoneNoneAllAllAny FtPHLABor Cn+ Mode Test Table 2 Function Inputs S1 = S2 = , S0 = S3 = M = 0 VLogic Mode Test Table 3 Function Inputs S1 = S2 = M = , S0 = S3 = 0 VInputOther InputOther Data InputsOutputSymbolUnderSame , CntPLHBANoneRemainingRemainingFitPHLAB, CntPLHANoneBNoneRemainingPtPHLA and B, CntPLHBANoneNoneRemainingPtPHLA and B, CntPLHABNoneNoneRemainingGtPHLA and B, CntPLHBNoneANoneRemainingGtPHLA and B, CntPLHANoneBRemainingRemainingA = BtPHLAB, CntPLHBANoneRemainingRemainingA = BtPHLAB, CntPLHABNoneNoneRemainingCn+4tPHLA and B, CntPLHBNoneANoneRemainingCn+4tPHLA and B.

7 CntPLHCnNoneNoneAllNoneCn+4tPHLA and BInputOther InputOther Data InputsOutputSymbolUnderSame FtPHLA and B, CntPLHBANoneNoneRemainingAny FtPHLA and B, 4-Bit Arithmetic Logic UnitPhysical Dimensions inches (millimeters) unless otherwise noted24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, WidePackage Number N24 AFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and SUPPORT POLICYFAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1. Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or