DP83867IR/CR High Immunity 10/100/1000 …

1 DP8386710/100/ 1000 MbpsEthernet Physical LayerEthernet MACM agneticsRJ-45 StatusLEDs25 MHzCrystal or OscillatorMII (PAP)GMII (PAP)RGMII (PAP, RGZ)10 BASE-Te100 BASE-TX1000 BASE-TProductFolderOrderNowTechnicalDocu mentsTools &SoftwareSupport &CommunityAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand ,DP83867 CRSNLS484E FEBRUARY2015 REVISEDMARCH2017DP83867IR/CRRobust,High Immunity10/100/ 1000 EthernetPhysicalLayer Transceiver11 Features1 UltraLow RGMIIL atencyTX < 90ns,RX < 290ns Low Powerconsumption457 mW Exceeds8000V IEC 61000-4-2 ESDP rotection MeetsEN55011 ClassB EmissionStandards 16 ProgrammableRGMIID elayModeson RX/TX IntegratedMDI TerminationResistors ProgrammableMII/GMII/RGMIIT erminationImpedance WoL(Wake-on-LAN)PacketDetection 25-MHzor 125-MHzSynchronizedClockOutput IEEE1588 TimeStampSupport RJ45 MirrorMode FullyCompatibleto ,100 BASE-TX,and 1000 BASE-TSpecification CableDiagnostics MII, GMIIand RGMIIMACI nterfaceOptions ConfigurableI/O Voltage( V, V, V) FastLink up / Link DropModes JTAGS upport2 Applications Motorand MotionControl IndustrialFactoryAutomation IndustrialEmbeddedComputing Wiredand WirelessCommunicationsInfrastructure Testand Measurement ConsumerElectronics3 DescriptionTheDP83867deviceis a robust,low power,fullyfeaturedPhysicalLayertranscei verwithintegratedPMDsublayersto support10 BASE-Te,100 BASE-TXand ,the DP83867exceeds8-kVIEC61000-4-2(directcon tact).

2 The DP83867is designedfor easyimplementationof10/100 interfacesdirectlyto twistedpairmediavia an theMAClayerthroughthe (MII),the (GMII)or ReducedGMII(RGMII).The QFPpackagesupportsMII/GMII/RGMII whereasthe ,includinga has low latencyand providesIEEE1588 Startof (PAP)and457mW(RGZ)underfull (1)PARTNUMBERTEMPERATUREPACKAGEBODYSIZE( NOM)DP83867 IRPAP 40 C to +85 CQFP(64)10 mm x 10 mmDP83867 IRRGZ 40 C to +85 CQFN(48)7 mm x 7 mmDP83867 CRRGZ0 C to +70 CQFN(48)7 mm x 7 mm(1) For all availablepackages,see the orderableaddendumatthe end of the ,DP83867 CRSNLS484E FEBRUARY2015 :DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporatedTableof Contents1 Pin Configurationand FrameDetectionTiming. Applicationand Deviceand Mechanical,Packaging,and , FEBRUARY2015 REVISEDMARCH2017 ProductFolderLinks:DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporated4 RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (July2016)to RevisionEPage ChangedINT / PWDN descriptioninPin AddedDP83867IR/CRStartof AddedsectionSFDL atencyVariationand Addeda statementto ChangedTable9.

3 48 Changedbit 8:7 fromRO to RW inConfigurationRegister4 (CFG4)..83 AddedSkewFIFOS tatus(SKEW_FIFO) Addednoteto STRAP_CLK_OUT_DISbit in Table44 AddedSyncFIFOC ontrol(SYNC_FIFO_CTRL) ClarifiedFigure30 ..110 ChangesfromRevisionC (November2015)to RevisionDPage Added'(StrapsRequired)' to RX_DV/RX_CTRLpin inPin Changed'1nF' to '1 F' forVDD1P1andVDD1P0pin inPin ChangedparametersymbolfromVIH to AddedMDCtogglingclarificationtoResetTimi ng(2)..16 Changedtargetstrapvoltagethresholdsin Table4 ..45 Changed'SPEED_SEL1' to 'ANEG_SEL1' in Table5 ..46 Added'(StrapsRequired)' to RX_DV/RX_CTRLin Changed'SPEED_SEL0' to 'ANEG_SEL' in Table5 ..47 Changed'SPEED_SEL0' to 'ANEG_SEL0' in Table5 ..47 Changedtablenamefrom'PAPS peedSelectStrapDetails' to Changed'SPEED_SEL0' and 'SPEED_SEL' to 'ANEG_SEL0' and 'ANEG_SEL1' in Table6 ..48 Changedtablenamefrom'RGZS peedSelectStrapDetails' to Table7 ..48 Changed'SPEED_SEL' to 'ANEG_SEL' in Table7 ..48 ChangedDefaultstateof from'Strap' to '0' for bit 13 in ChangedDefaultstateof from'Strap' to '1' for bit 6 in Changedbit 9 namefrom100 BASE-TFULLDUPLEXto 1000 BASE-TFULLDUPLEXin Changedbit 9 descriptionsfromhalf duplexto full duplexin Changed'InterruptStatusand EventControlRegister(ISR)' to 'MII InterruptControlRegister(MICR)' inMIII nterruptControlRegister(MICR).

4 70 ChangedRegisterdefinitionto movea statementfromInterruptStatusRegister(ISR )toMII InterruptControlRegister(MICR)..70 Changeddefaultof bit 9 from'1' to '0' inConfigurationRegister2 (CFG2), Changeddefaultof bits 5:0 from'0' to '0 0111' in Table28 ..74 AddedFastLink DropConfigurationRegister(FLD_CFG) ChangedNameof Bits 6:5 from'STRAP_SPEED_SEL' to 'STRAP_ANEG_SEL' in ChangedNameof Bit 6 from'RESERVED' to 'RESERVED(RGZ)' in Table44 ..86 ChangedNameof Bit 5 from'STRAP_SPEED_SEL(PAP)' to 'STRAP_SPEED_SEL(RGZ)' in Changednameof Bit 6:4 from'RESERVED' to 'RESERVED(PAP)' in Table45 ..874DP83867IR,DP83867 CRSNLS484E FEBRUARY2015 :DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporated Addeddescriptionfor 'STRAP_RGMII_CLK_SKEW_TX(RGZ)' in Table45 ..87 Changednameof Bit 2:0 from'RESERVED' to 'RESERVED(PAP)' in Table45 ..87 Addeddescriptionfor 'STRAP_RGMII_CLK_SKEW_RX(RGZ)' in Table45 ..87 Changeddefaultvalueof bit 4:0 from'10000' to 'TRIM' inI/O Configuration(IO_MUX_CFG).

5 97 Changeddescriptionfor IO_IMPEDANCE_CTRL bits inI/O Configuration(IO_MUX_CFG)..97 Added"The comeup with or afterthe not beforeit" AddedFigure35 ..115 AddedTable126 ..115 no load existson (August2015)to RevisionCPage Changedthe title to add DP83867 IRRGZ/CRRGZin the Addedpart ChangedlatencybulletpointinFeaturesfor betterdescriptionof the Low AddedMDI AddedProgrammableMACI nterfaceImpedancein ..1 Added'RJ45 MirrorMode' AddedPackageinformationfor the new devicesin ChangedPin Functionstableto add informationaboutnew Addedinformationaboutpull-uppull-downres istorsin the tablenoteof thePin Changedbypasscapacitorinformationfor powerpins inPin AddedESDinformationaboutnew Addedthermalinformationfor AddedPMDoutputvoltagedatafor new AddedRGMIITX and RX LatencyvaluesinRGMIIT iming(4)..16 AddedFBDfor new Added"MagicPacketshouldbe byte aligned" Changed"Auto-MDIXis independentof Auto-Negotiation" to "For 10/100,Auto-MDIXis independentof Auto-Negotiation" Changed"improperly-terminatedcableswith 1m accuracy" to "improperly-terminatedcables,and crossedpairswireswith 1m accuracy" Added" 1000 Mmode" inFastLink Deletedmentionof FLD_CFGand FLD_THR_CFGfromFastLink , FEBRUARY2015 REVISEDMARCH2017 ProductFolderLinks:DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporated AddedAddedinternalresistorto the diagraminFigure24.

6 45 AddedTargetvoltagerangein Addedstrappinginformationfor RGZdevicesin Table5 ..46 Changedincorrectpin numberfor LED_1and LED_0in Table5 AddedRGMIITX and RX SkewStrapinformationto Table5 ..47 AddedTable7 ..48 AddedTable8 ..48 AddedTable9 ..48 Addedinformationregardingaddressconfigur ationof ChangedBit 13 Deleted"in RobustAutoMDI-Xmodes" in bit 15 descriptionofConfigurationRegister3 (CFG3)..80 Added"ms" to timervaluesin bit 13:12inConfigurationRegister3 (CFG3)..80 DeletedRegistersFLD_CFGand Changeddescriptionfor bit 11 in100 BASE-TXConfiguration(100CR)..85 Addedinformationin bit 10:7descriptionfor100 BASE-TXConfiguration(100CR)..85 AddedcommentaboutRGZdevicesinGPIOMux ControlRegister1 (GPIO_MUX_CTRL1)..98 AddedcommentaboutRGZdevicesinGPIOMux ControlRegister2 (GPIO_MUX_CTRL2)..100 AddedGPIO_MUX_CTRL registerfor Addedfootnoteaboutvoltagelevelfor RGZdevicesin AddedCommentfor VDDA1P8pins in Figure33..113 AddedfootnoteaboutVoltagelevelfor RGZdevicesin (June2015)to RevisionBPage Added"Powerconsumptionas low as 490 mW" to theFeatureslist.

7 1 ChangedDescriptiontext From:"The DP83867consumesonly 565 mW" To: "The DP83867consumesonly 490 mW" .. 1 ChangedPin RBIASD escriptionFrom:"A 10 k +/-1%resistor" To: "A 11 k 1% resistor"..12 ChangedPowerconsumption,2 suppliesTYPvalueFrom565 mW To 530 mW in ChangedPowerconsumption,optional3rd supplyTYPvalueFrom545 mW To 490 mW in ChangedRegisteraddress:From:"BICSR1regis ter(0x0039)" To: "BICSR2register(0x0072)", and changedFrom:"readfromthe BISCR register(0x0016h)" To: "readfromthe STS2register(0x0017h)" in ChangedsectionBISTC ontroland StatusRegister1 (BICSR1)and Table46 From:Address0x0039To: ChangedsectionBISTC ontroland StatusRegister2 (BICSR2)and Table47 From:Address0x003 ATo: ,DP83867 CRSNLS484E FEBRUARY2015 :DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporatedChanges fromOriginal(February2015)to RevisionAPage Changedthe documenttitle From:"Robust,Low Power" To: "Robust,HighImmunity" ..1 ChangedtheFeatureslistedunder"Highlights ".

8 1 ChangedtheApplicationslist ..1 ChangedtheDescriptiontext and AddedTFfall time = (Max)inRGMIIT iming(4)..16 AddedT4, MDI to GMIIL atency= 264 ns (NOM)toGMIIR eceiveTiming(6)..17 Changedthe title of Figure23 From:TypicalMDC/MDIOReadOperationTo: FastLink Movedtext Fromthe end of Table10 ToPHYI dentifierRegister#1 (PHYIDR1)..57 Changedformatof loopbackcontrolbits in Table30 "BISTC ontrolRegister(BISCR)" ..75 ChangedBIT NAME(11:8)From:"LED_ACT_SELTo: LED_2_SELin Table32 ..77 ChangedBIT NAME(7:4)From:"LED_SPD_SELTo: LED_1_SELin Table32 ..78 ChangedBIT NAME(3:0 From:"LED_LNK_SELTo: LED_0_SELin Table32 ..78 Changedthe title of Table45 from:Address0x006 FEto: Changeddefaultof bits 12:8to 0 1100in Table96 ..97 Deletedtext "of the 64-HTQFP package" fromthe secondparagraphin sectionCableLine Deletedtext "for MII Mode" fromthe secondparagraphin sectionClockIn (XI) 18 19 20 21 22 23 2436353433323130292827262512345678910111 264 63 62 61 60 59 58 574950515253545556RX_D3RX_D2RX_D1RX_D0RX _CLKVDD1P1 GTX_CLKTX_D1TX_D2TX_D3TX_D4TD_P_ATD_M_AV DDA2P5TD_P_BTD_M_BTD_P_CTD_M_CVDD1P1 VDDA2P5TD_P_DTD_M_DRBIASVDDIOLED_0 LED_1 LED_2 INT/PWDNRESET_NVDD1P1CS/GPIOCOL/GPIORX_D V/RX_CTRLRX_ER/GPIOVDDA1P8X_OX_IMDCMDIOV DDIOCLK_OUTJTAG_CLKJTAG_TDOJTAG_TMSJTAG_ TDIVDD1P1 RESERVEDRESERVEDRESERVEDRESERVEDTX_CLKTX _D7TX_D6RX_D4/GPIOVDDIOTX_ERTX_D5TX_EN/T X_CTRLRXD_7/GPIORX_D5/GPIORX_D6/GPIOVDDA 1P8 JTAG_TRSTNTX_D07DP83867IR, FEBRUARY2015 REVISEDMARCH2017 ProductFolderLinks:DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporated5 DeviceComparisonTable1.)

9 DeviceFeaturesComparisonDEVICEMACTEMPERA TURERANGETEMPERATUREGRADEDP83867 CRRGZRGMII0 C70 CCommercialDP83867 IRRGZRGMII 40 C85 CIndustrialDP83867 IRPAPMII/GMII/RGMII 40 C85 CIndustrial6 Pin Configurationand FunctionsPAPP ackage64-PinHTQFPTop ViewDP83867 TOP VIEW(not to scale)48-pin QFN PackageDAP = GNDRBIASVDD1P0 LED_0 LED_1 LED_2 INT/PWDNRESET_NVDDIOGPIO_1 GPIO_0TX_CTRLRX_CTRLRX_D3RX_D2RX_D1RX_D0 RX_CLKVDD1P0 VDDIOGTX_CLKTX_D0TX_D1TX_D2TX_D3 VDDA1P8X_OX_IMDCMDIOVDDIOCLK_OUTJTAG_CLK JTAG_TDOJTAG_TMSJTAG_TDIVDD1P0TD_P_ATD_M _AVDDA1P8 VDDA2P5TD_P_BTD_M_BTD_P_CTD_M_CVDD1P0 VDDA2P5TD_P_DTD_M_D123456789101112131415 1617181920212223243635343332313029282726 254847464544434241403938378DP83867IR,DP8 3867 CRSNLS484E FEBRUARY2015 :DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporatedRGZP ackage48-PinQFNTop View9DP83867IR, FEBRUARY2015 REVISEDMARCH2017 ProductFolderLinks:DP83867 IRDP83867 CRSubmitDocumentationFeedbackCopyright 2015 2017,TexasInstrumentsIncorporated(1)The functionalitiesof the pins are definedbelow.

10 (a) TypeI: Input(b) TypeO: Output(c) TypeI/O: Input/Output(d) TypePD or PU: InternalPull-downor Pull-up(e) TypeS: StrapConfigurationPin(f) Type:A AnalogpinsNOTE:InternalPull-Up/Pull-Down resistorson the IO pins are disabledwhenthe FunctionsPINTYPE(1)DESCRIPTIONNAMEHTQFPV QFNMACINTERFACESRGMII,GMII,MIIRGMIITX_CL K30 OMII TRANSMITCLOCK:TX_CLKis a continuousclocksignaldrivenbythe PHYduring10 Mbpsor 100 MbpsMII errorout of the MAClayerand into the TX_CLKclockfrequencyis MHzin 10 BASE-Teand 25 , PDGMIITRANSMITDATABit 7: This signalcarriesdatafromthe MACtothe PHYin is synchronousto the , PDGMIITRANSMITDATABit 6: This signalcarriesdatafromthe MACtothe PHYin is synchronousto the , PDGMIITRANSMITDATABit 5: This signalcarriesdatafromthe MACtothe PHYin is synchronousto the , PDGMIITRANSMITDATABit 4: This signalcarriesdatafromthe MACtothe PHYin is synchronousto the , PDTRANSMITDATABit 3: This signalcarriesdatafromthe MACto thePHYin GMII,RGMII,and MII GMIIand RGMII modes,it issynchronousto the MII mode,it issynchronousto the , PDTRANSMITDATABit 2: This signalcarriesdatafromthe MACto thePHYin GMII,RGMII,and MII GMIIand RGMII modes,it issynchronousto the MII mode,it issynchronousto the , PDTRANSMITDATABit 1: This signalcarriesdatafromthe MACto thePHYin GMII,RGMII,and MII GMIIand RGMII modes,it issynchronousto the MII mode,it issynchronousto the , PDTRANSMITDATABit 0: This signalcarriesdatafromthe MACto thePHYin GMII,RGMII,and MII GMIIand RGMII modes,it issynchronousto the MII mode,it issynchronousto the , PDGMIITRANSMITERROR.