DRAM Design Overview - Computer Graphics at Stanford ...

1 Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview DRAM Design Overview Stanford University Junji Ogawa Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Contents Trends of Standard DRAM. History of DRAM Circuits Cell, Array and Major Circuits Embedded DRAM. ASM Example Summary Feb. 11th. 1998 Junji Ogawa Page 1. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview Standard DRAM Development 4G. 1000. 1G. 500 256M 4G. Conference Early Production 64M. Die Size(mm2). 200. 256M Production 100 64M. 16M 128M. 50 1G. i-line KrF KrF+ ArF ? Rule (um). 20. 90 92 94 96 98 00 02 04 06 08 10. Year Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Bit Cost Trend of DRAMs 4 -0. 10 10. 3 -1. 10 10. size Die Density Mbits). ity Die Size mm2). Bit Cost $ . 2 -2. 10 ns 10. Rule m . De 1 -3. 10 10. Bit Cost 0 -4. 10 Rule 10. -1 16M -5. 10 64M 10. 256M. 1G. -2. 4G -6. 10 10. 1980 1985 1990 1995 2000 2005 2010 Year Feb.

2 11th. 1998 Junji Ogawa Page 2. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview Access Time Trend f CLK (Popular Synchronous Frequency :MHz). 2 9. 10 10. 1/tAA (/CAS Access Frequency :MHz). TRAC (/RAS Access Time :ns). Power Supply Voltage (V). VCCx10. TRAC. 8. 10. 1 10. 1/tAA. f CLK. 7. 1 10. 4M 16M 64M 256M 1G 4G. Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Standard DRAM Column Access Mode Product Volume [ 100 million ]. 25 -- ? FPM >128M. 64M SD. 20 -- SD. 64M RD. Rambus 16M. EDO SD SDRAM. 10 -- 16M EDO. 4M. 0 -- '97 '98 '99 2000. Year Feb. 11th. 1998 Junji Ogawa Page 3. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview DRAM Operating Frequency Customizability ASSP/ASIC. Function rich DRAM. Customizability DRAM/Logi c WRAM. CDRAM High-speed VRAM MDRAM DRAM. Standard EDRAM SLDRAM. DDR. RAMBUS Target SDRAM. EDO. 100 MHz 200 MHz 500 MHz 1 GHz 2 GHz Operating Frequency Feb.

3 11th. 1998 Junji Ogawa DRAM Design Overview VCC & VII & WL Voltage Trend Internally Regulated Supply Voltage(v). 8 Internally Regulated Supply Voltage(V). Power Supply Voltage (V). Word Boost Level(V). 6. Power Supply Voltage (v). Word Boost Voltage (v). 4. 2. 0. 4M 16M 64M 256M 1G 4G. Bit Density Feb. 11th. 1998 Junji Ogawa Page 4. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview Power Dissipation Trend 1 1. 10 10. Active Power tRC=min. (A) VCC. Power Supply Voltage (V). ( Low Power mode: mA). Low Power 0 0. 10 Stand-by Power 10. Stand-by Power -1 -1. 10 10. Active Power -2 -2. 10 10. 4M 16M 64M 256M 1G 4G. Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Refresh Specification Trend Numbers of Active S As Refresh Interval (max.:ms). Numbers of Active Sense Amplifiers Refresh Cycles Busy Rate ( s). Distributed Refresh Interval 5 3. 10 10. Distributed Refresh Interval Refresh Interval (max.)

4 :ms). 4 2. 10 10. Busy Rate ( S). Refresh Cycles 3 1. 10 10. 2 0. 10 10. 1M 4M 16M 64M256M 1G 4G. Feb. 11th. 1998 Junji Ogawa Page 5. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview History 1K DRAM Intel 1103 introduced late 1971. -3Tr PMOS, 1P1M, -Vdd=0v,Vss=16v,Vbb=20v, Trac=300ns 4K DRAM TI TMS4030 introduced 1973. -1Tr NMOS, 1P1M, TTL I/O. -Vdd=12v,Vdd=5v, Vss=0v,Vbb=-3/-5v 16K DRAM Mostek MK4116 introduced 1977. -1Tr NMOS, 2P1M, Address multiplex -Vdd=12v,Vdd=5v, Vss=0v,Vbb=-5v, Trac=250ns **Open / Folded bit line, Double poly cell, Multi-PS. Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Bascic Bitline Structure (1). Open Bitlines Folded Bitlines Memory Memory /BL BL. BL. Array Array WL WL. S/As S/As Open BL Folded BL. Memory Array Cell Size 6F2 Cell Size 8F2. /BL WL pitch: 3F WL pitch: 4F. BL pitch: 2F BL pitch: 2F. Denser Memory Relaxed S/A layout pitch Uneven WL coupling Even WL coupling Feb.

5 11th. 1998 Junji Ogawa Page 6. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview History (cont'd). 64K DRAM ('80,conference'79). -Many changes at once - no dominant Design -Standardized, Page mode, Refresh functions -Vcc=5v only,Vss=0v,Internal Vbb, Trac=200ns -Boosted wordline, Active restore 256K DRAM ('83,conference'82). -1Tr NMOS, 3P1M(FJ), mask increasing -Vcc=5v only, Nibble/SC/CBR func., Trac=150ns -Open Folded, Redundancy, CMOS prototype -Vdd bitline pre-charge -Some ASM, Wide I/O (x4). Feb. 11th. 1998 Junji Ogawa DRAM Design Overview History (cont'd). 1M DRAM ('86,conference'84). -N-well CMOS, 3P1M, Vdd/2 cell plate -Half Vdd bitline reference and pre-charge, -Shared folded bitline -x4/x8, Package and module variety, Test circuits 4M DRAM ('89, conference'87). -3D stacked or trench cell, CMOS, 4P1M, -x16, Fast page/Self refresh, Trac=80ns -Current-mirror data bus amp., Boosted I/O driver -Word line strapping, Triple-well Feb.

6 11th. 1998 Junji Ogawa Page 7. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview Basic Bitline Structure (2). Interleaved (Multiplexed). Folded Shared S/As BLs Memory /BLU BLU Memory Array Array WLU WLU. S/As S/As WLL WLL. Memory Array Memory /BLL BLL BLL. Array Less area occupied S/As by S/As Used in nearly all 16M. Relaxes S/A pitch Feb. 11th. 1998 Junji Ogawa DRAM Design Overview History (cont'd). 16M DRAM ('92, conference'90). -N-well CMOS, 4P2M. -Internal Vdd down-converter (5v int.). -Shared Y-decoder, Interleaved S/A, -Vpp supply WL driver, RDRAM(PLL/DLL). 64M DRAM ('95, conference '91). -Triple well CMOS, Vss Substrate, 4P2M, -Vdd= , Separate I/O PS-pin (Vddq/Vssq). -SDRAM (clocked In, pipelined, burst I/O, term. I/F). -COB, Staggered Sense amp. Feb. 11th. 1998 Junji Ogawa Page 8. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview Circuit Evolution Picking up 3Tr to 1Tr1C Address Multiplex Boosted Wordline Open BL to Folded BL.

7 Single Power Supply NMOS to CMOS. (Vbb gene., WL boost) Page & Refresh Mode Redundancy Appli. Specific Circuits Vdd/2 BL pre-charge (ex. SR for VRAM). Internal DC converter Test mode Clocked operation Pipelined operation PLL/DLL High speed interface Multi-bank core Embedded core Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Cell Array and Circuits (1) 1 Transistor 1 Capacitor Cell Size Comparison to SRAM Cell (2) Array Example (3) Major Circuits (today's example). Sense amplifier Dynamic Row Decoder Wordline Driver The other circuits interesting for VLSI designer Data bus amplifier Voltage Regulator Reference generator Redundancy technique Replica technique High speed I/O circuits Feb. 11th. 1998 Junji Ogawa Page 9. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview SRAM DRAM. 6Tr embedded SRAM 1Tr1C Standard DRAM. WL Access Tr (Cell Tr, Transfer Tr). WL Cwb Storage Node Cs Cbl BL /BL BL.

8 Plate Gain element in cell Passive element (No gain, Refresh needed). Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Comparison of SRAM and DRAM Cell Size 100. 6Tr SRAM. Plainer Cell Size [um2]. 10. 3Tr 1. Stack DRAM. Design Rule [um]. Feb. 11th. 1998 Junji Ogawa Page 10. MH students Feb. 11th. 1999. 8 global data buses 32M-CELL BLOCK. S/A). 4096S/A+16R**S/A+64 Red-S/A+16 Mark-RAM(64. Mark-RAM. (4S/A. K)for 64 100%. + + + =. CL). (1024. 32 Mbit array. 4R**S/. A 1024S/A+4R**S/A. +16 Red-S/A+4 Mark-RAM. 7. A. 4 Red-S/. A. 256S/ Sub-Word Decoder A. 256S/. MWDEC (256CL). MWDEC s/a- 0. MWL. 256. 256K Cell Array 1M BLOCK #0. Standard DRAM Array Design Example 1. s/a- DQ. MWL. DRAM Array Example 64K 1M BLOCK #1. Junji Ogawa Junji Ogawa 0. s/a- 2. 8 global data buses 1M BLOCK #2. s/a- 3. and 8 amplifiers 1M BLOCK #3. s/a- 4. 1M BLOCK #4. 64 Mbit DRAM. 32 Mbit arrays 5. s/a- consists of two 1M BLOCK #5. s/a- 6. 1M BLOCK #6.

9 S/a- 7. 1M BLOCK #7. s/a- 8. Main Word Decoder / Driver Page 11. 1M BLOCK #8. 9. s/a- 1M BLOCK #9. bank 0 bank 8 bank 0 bank 8. s/a-1. 0. 15. 1M BLOCK #10. 64 Mbit Core, a part of 256M DRAM. 32 Mbit 15. s/a-1. 1. 1M BLOCK #11. s/a-1. 2. DQ. 7. 8. s/a-2. 6. 15. 1M BLOCK #26. 32 Mbit 7 s/a-2. 7. 1M BLOCK #27. s/a-2. 8. 1M BLOCK #28. DQ. 9. s/a-2. 0. 7. Stanford CS Junji Ogawa RCL 1M BLOCK #29. DRAM Design Overview DRAM Design Overview s/a-3. 0. CL 1M BLOCK #30. Mark Out s/a-3. 1. 1M BLOCK #31. 2. s/a-3. s/a- . 0 RowBLOCK. 128K Spare #R. Feb. 11th. 1998. Feb. 11th. 1998. s/a- . 1. C-DEC. C-DEC. (64CL) C-DEC. (64CL) C-DEC. (64CL) (64CL)C-DEC. C-DEC. (64CL) C-DEC. (64CL) C-DEC. (64CL) (64CL) Column Decoder Driver &. (256CL). COL. DECODER. EOR EOR & etc. Mark(forCOL. & Add RAM. ). Address Mark RAM. & Spare Col. Mark& Mark Add RAM & Add. RAM. (for 64K) Driver Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview DRAM Array Example (cont'd).

10 Interleaved S A & Hierarchical Row Decoder/Driver (shared bit lines are not shown). Nmat SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. Q. P. Q. P. P. P. P. Clump TR or so Main Row Dec SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. SA. Q. P. P. P. P. Q. P. 512K Array Nmat=16 or 12. ( 256 WL x 2048 SA). Feb. 11th. 1998 Junji Ogawa DRAM Design Overview Row Decoder and Driver WL Strapping Type . Clump TR or so Main Row Dec VCC. Addresses WDi Contact only (Strapping). Reset AL strap line Dynamic P1 word line NAND. Feb. 11th. 1998 Junji Ogawa Page 12. Stanford CS Junji Ogawa MH students Feb. 11th. 1999. DRAM Design Overview Row Decoder and Driver (cont'd). Hierarchical WL Type . VPP. /pre#. Clump TR or so level MWL. Main Row Dec /rbnk# shifter Pre-decode address # is bank No. MWDEC. Sub Word Decoder AL Main Word Line VPP WDij WDik WDil WDim Reset Reset Reset Reset Addresses VPP . Reset P1 sub-word line P.