DRV8844 Quad ½-H-Bridge Driver IC (Rev. D) - …

1 Product Sample & Technical Tools & Support &. Folder Buy Documents Software Community DRV8844 . SLVSBA2D JULY 2012 REVISED MAY 2016. DRV8844 Quad -H- bridge Driver IC. 1 Features 3 Description 1 Quad 1/2-H- bridge DC Motor Driver The DRV8844 provides four individually controllable 1/2-H- bridge drivers. It can be used to drive two DC. Can Drive Four Solenoids, Two DC Motors, motors, one stepper motor, four solenoids, or other One Stepper Motor, or Other Loads loads. The output Driver channel for each channel Full Individual Half bridge Control consists of N-channel power MOSFET's configured in Low MOSFET On-Resistance a 1/2-H- bridge configuration. Maximum Drive Current at 24 V, 25 C The DRV8844 can supply up to peak or Floating Input Buffers Allow Dual (Bipolar) RMS output current per channel (with proper PCB. Supplies (up to 30 V) heatsinking at 24 V and 25 C) per H- bridge . Built-In , 10-mA LDO Regulator Separate inputs to independently control each 1/2-H- bridge are provided.

2 To allow operation with split Industry Standard IN/IN Digital Control Interface supplies, the logic inputs and nFAULT output are 8-V to 60-V Operating Supply Voltage Range referenced to a separate floating ground pin. Outputs Can Be Connected in Parallel Internal shutdown functions are provided for over Thermally Enhanced Surface Mount Package current protection, short circuit protection, undervoltage lockout, and overtemperature. 2 Applications The DRV8844 is available in a 28-pin HTSSOP. Textile Machines package with PowerPAD (Eco-friendly: RoHS & no Office Automation Machines Sb/Br). Gaming Machines Device Information(1). Factory Automation PART NUMBER PACKAGE BODY SIZE (NOM). Robotics DRV8844 HTSSOP (28) mm mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic 8 to 60 V. DRV8844 A. +. 8 EN / IN BDC M. 4 Half-H.. SLEEP. Controller Bridges A + . FAULT. Protection BDC.

3 MOSFETs Copyright 2016, Texas Instruments Incorporated 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV8844 . SLVSBA2D JULY 2012 REVISED MAY 2016 Table of Contents 1 Features .. 1 8 Application and Implementation .. 12. 2 Applications .. 1 Application 12. 3 Description .. 1 Typical Application .. 12. 4 Revision 2 9 Power Supply 15. 5 Pin Configuration and Functions .. 3 Bulk Capacitance .. 15. 6 4 10 16. Absolute Maximum Ratings .. 4 Layout Guidelines .. 16. ESD Ratings .. 4 Layout Example .. 16. Recommended Operating 4 Thermal Considerations .. 16. Thermal Information .. 5 Power Dissipation .. 17. Electrical 5 11 Device and Documentation Support .. 18. Switching Characteristics .. 6 Documentation Support .. 18. Typical Characteristics .. 7 Community 18. 7 Detailed Description.

4 8 Trademarks .. 18. Overview .. 8 Electrostatic Discharge Caution .. 18. Functional Block Diagram .. 8 Glossary .. 18. Feature 9 12 Mechanical, Packaging, and Orderable Device Functional 11 Information .. 18. 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (May 2015) to Revision D Page Added parallel output connection to the Features section .. 1. Changed pins 6 and 9 from VNEG to SRC12 and SRC34 (respectively) in the Pin Configuration and Functions section .. 3. Added SRC12, SRC34 to VNEG pins parameter to the Absolute Maximum Ratings table .. 4. Changed the Functional Block Diagram to show the change of pin 6 and 9 from VNEG to SRC12 and SRC34 .. 8. Added parallel output description and sense-resistor option to the Application Information section .. 12. Changes from Revision B (January 2015) to Revision C Page Added ambient temperature to Recommended Operating Conditions.

5 4. Changes from Revision A (October 2012) to Revision B Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .. 4. 2 Submit Documentation Feedback Copyright 2012 2016, Texas Instruments Incorporated Product Folder Links: DRV8844 . DRV8844 . SLVSBA2D JULY 2012 REVISED MAY 2016. 5 Pin Configuration and Functions PWP Package 28-Pin HTSSOP. Top View CP1 1 28 VNEG. CP2 2 27 IN1. VCP 3 26 EN1. VM 4 25 IN2. OUT1 5 24 EN2. SRC12 6 23 IN3. OUT2 7 GND 22 EN3. (PPAD). OUT3 8 21 IN4. SRC34 9 20 EN4. OUT4 10 19 LGND. VM 11 18 nFAULT. NC 12 17 nSLEEP. NC 13 16 NRESET. VNEG 14 15 V3P3 OUT. Pin Functions PIN. TYPE (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS. NAME NO. POWER AND GROUND. CP1 1 P Charge pump flying capacitor Connect a F 100-V capacitor between CP1 and CP2.

6 CP2 2 P Charge pump flying capacitor Connect to logic ground. This may be any voltage between VNEG. LGND 19 P Logic input reference ground and VM 8 V. Bypass to VNEG with a F ceramic capacitor. Can be V3P3 OUT 15 P regulator output used to supply VREF. VCP 3 P High-side gate drive voltage Connect a F 16-V ceramic capacitor to VM. Connect to motor supply (8 V to 60 V). Both pins must be VM 4, 11 P Main power supply connected to same supply. Bypass to VNEG with a 10- F. (minimum) capacitor. Low-side FET source for OUT1. SRC12 6 P. and OUT2 Connect to VNEG directly or through optional current-sense Low-side FET source for OUT3 resistor SRC34 9 P. and OUT4. Negative power supply (dual 14, 28, VNEG P supplies) or ground (single PPAD. supply). CONTROL. EN1 26 I Channel 1 enable Logic high enables OUT1. Internal pulldown. EN2 24 I Channel 2 enable Logic high enables OUT2. Internal pulldown. EN3 22 I Channel 3 enable Logic high enables OUT3.

7 Internal pulldown. EN4 20 I Channel 4 enable Logic high enables OUT4. Internal pulldown. IN1 27 I Channel 1 input Logic input controls state of OUT1. Internal pulldown. IN2 25 I Channel 2 input Logic input controls state of OUT2. Internal pulldown. IN3 23 I Channel 3 input Logic input controls state of OUT3. Internal pulldown. IN4 21 I Channel 4 input Logic input controls state of OUT4. Internal pulldown. Active-low reset input initializes internal logic and disables the H- nRESET 16 I Reset input bridge outputs. Internal pulldown. Logic high to enable device, logic low to enter low-power sleep nSLEEP 17 I Sleep mode input mode. Internal pulldown. (1) I = input, O = output, OD = open-drain output, P = power Copyright 2012 2016, Texas Instruments Incorporated Submit Documentation Feedback 3. Product Folder Links: DRV8844 . DRV8844 . SLVSBA2D JULY 2012 REVISED MAY 2016 Pin Functions (continued). PIN. TYPE (1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS.

8 NAME NO. STATUS. Logic low when in fault condition (overtemperature, overcurrent, nFAULT 18 OD Fault UVLO). Open-drain output. OUTPUT. OUT1 5 O Output 1. OUT2 7 O Output 2. Connect to loads OUT3 8 O Output 3. OUT4 10 O Output 4. NO CONNECT. NC 12, 13 No connect No connection to these pins 6 Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1). MIN MAX UNIT. VM Power supply voltage 65 V. Logic ground voltage (LGND) VM - 8 V. Digital pin voltage LGND LGND + 7 V. SRC12, SRC34 (pins 6 and 9 with optional sense resistor) to VNEG pins (pins 14 and V. 28). Peak motor drive output current, t < 1 s Internally limited A. Continuous motor drive output current (2) A. TJ Operating virtual junction temperature 40 150 C. Tstg Storage temperature 60 150 C. (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions.

9 Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Power dissipation and thermal limits must be observed. ESD Ratings VALUE UNIT. Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 3000. V(ESD) Electrostatic discharge V. Charged device model (CDM), per JEDEC specification JESD22-C101 (2) 1500. (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted). MIN NOM MAX UNIT. (1). VM Motor power supply voltage 8 60 V. IV3P3 V3P3 OUT load current 0 10 mA. TA Ambient temperature 40 125 C. (1) All VM pins must be connected to the same supply voltage. 4 Submit Documentation Feedback Copyright 2012 2016, Texas Instruments Incorporated Product Folder Links: DRV8844 .

10 DRV8844 . SLVSBA2D JULY 2012 REVISED MAY 2016. Thermal Information DRV8844 . THERMAL METRIC (1) PWP (HTSSOP) UNIT. 16 PINS. R JA Junction-to-ambient thermal resistance C/W. R JC(top) Junction-to-case (top) thermal resistance C/W. R JB Junction-to-board thermal resistance C/W. JT Junction-to-top characterization parameter C/W. JB Junction-to-board characterization parameter C/W. R JC(bot) Junction-to-case (bottom) thermal resistance C/W. (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Electrical Characteristics TA = 25 C, over operating free-air temperature range, all voltages relative to VNEG terminal (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT. POWER SUPPLIES. IVM VM operating supply current VM = 24 V, fPWM < 50 kHz 1 5 mA. IVMQ VM sleep mode supply current VM = 24 V 500 800 A. VUVLO VM undervoltage lockout voltage VM rising 8 V.