DS80PCI800 2.5-Gbps / 5.0-Gbps / 8.0-Gbps 8 …

1 VDD ( V)INA_0+INA_0-AD0AD1AD2AD3 ENSMBSCL(2)READ_EN / SD_THSDA(2)OUTA_0+ (DAP)(1) Schematic shows connection for SMBus Slave Mode (ENSMB=1kohm to VDD) For SMBus Master Mode or Pin Mode configuration, the connections are different.(2) SMBus signals need to be pulled up elsewhere in the system.(3) Schematic requires different connections for V F (x5)SMBus Slave Mode(1)..INA_3+INA_3-OUTA_3+OUTA_3-VDD_S ELVIN ( V)INB_0+INB_0-OUTB_0+ +INB_3-OUTB_3+OUTB_3-RXDETRATEPRSNTFrom PCIe PRSNT signalAddress straps(pull-up to VIN orpull-down to GND)(1)1 (3)10 FALL_DONERESERVEDTo SMBus/I2 CHost Slave Mode(1)SMBus Slave Mode(1)DS80 PCI800 System BoardRoot ComplexAdd-in CardEnd PointDS80 PCI800 Board TracePCIeConnectorPCIeConnectorTXRXRXTX8 888 ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityDS80 PCI800 SNLS334G APRIL2011 RepeaterWith Equalizationand De-Emphasis1 Features2 Applications1 ComprehensiveFamily,ProvenSystem PCI ExpressGen-1,Gen-2,and Gen-3 Interoperability3 Description DS80 PCI102: x1 PCIeThe DS80 PCI800is a low-power,8-channelrepeaterGen-1,Gen-2,a nd Gen-3with4-stageinputequalization,andan outputde- DS80 PCI402.

2 X4 PCIeemphasisdriverto enhancethe reachof PCI-ExpressGen-1,Gen-2,and Gen-3seriallinksin board-to-boardor cableinterconnects. DS80 PCI800: x8/x16 PCIeThisdeviceis idealfor higherdensityx8 and x16 Gen-1,Gen-2,and Gen-3 PCI-Expressconfigurations,andit automaticallydetectsand adaptsto Gen-1,Gen-2,and Gen-3data AutomaticRateDetectand Adaptationto Gen-ratesfor SeamlessSupportfor Gen-3 TransmitFIRemphasis(upto 12 dB),transmitVOD(uptoHandshake1300mVp-p)a nd receiveequalization(up to 36 dB) ReceiverEQ (up to 36 dB), TransmitDe-to enablelongerdistancetransmissionin lossyEmphasis(up to 12 dB)coppercables(10 metersor more),or backplanes to Vp-p(Pin(40 inchesor more) )receivercan openan inputeye thatis completelycloseddueto inter-symbolinterference(ISI) UI of ResidualDeterministicJitterat 8 Gbpsintroducedby the Inchesof FR4 or 10 m 30-awgPCIeCableTheprogrammablesettingsca nbe appliedeasilythroughpinsor software(SMBus/I2C), or canbe Low PowerDissipationWithAbilityto.

3 65 mW/Channeloperatingin the EEPROM mode,the configuration AutomaticReceiverDetect(Hot-Plug)informa tionis automaticallyloadedon powerup, MultipleConfigurationModes:Pins/SMBus/Di rect-whicheliminatestheneedforanexternal EEPROML oadmicroprocessoror softwaredriver. Flow-ThruPinout:54-PinWQFN(10-mm DeviceInformation(1) , )PARTNUMBERPACKAGEBODYSIZE(NOM) or V (Selectable)DS80 PCI800 WQFN(54) 3 kV HBMESDR ating(1) For all availablepackages,see the orderableaddendumat 40 C to 85 C OperatingTemperatureRangethe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand APRIL2011 Applicationand Pin Configurationand Deviceand Mechanical,Packaging,and RevisionHistoryChangesfromRevisionF (April2013)to RevisionGPage AddedESDR atingstable,FeatureDescriptionsection,De viceFunctionalModes,ApplicationandImplem entationsection,PowerSupplyRecommendatio nssection,Layoutsection,DeviceandDocumen tationSupportsection,andMechanical,Packa ging, 2011 2015,TexasInstrumentsIncorporatedProduct FolderLinks.

4 DS80 PCI800 OUTB_0+OUTB_0-OUTB_1+RESERVEDRXDETALL_DO NE454443422625 DAP = GNDOUTB_1-INB_2+INB_2-56724212023 INA_3-8 INA_0+INA_0-VDDINA_1+9101112 INA_1-EQA0 INA_2+INA_2-13181415 INA_3+1617 OUTA_1+OUTA_1-EQA1 OUTA_2+363435 OUTA_2-OUTA_3+OUTA_3-333132 VINVDD_SELOUTB_3+OUTB_3-VDD414039 RATEOUTA_0+OUTA_0-3738 INB_0+INB_0-INB_1+INB_1-OUTB_2-OUTB_2+24 3 VDD50484749 ENSMB4651 INB_3+INB_3-SMBUS AND CONTROL302928SD_TH/READ_EN521922 PRSNT2715354 VDDVDDDEMA1/SCLDEMA0/SDADEMB1/AD0 DEMB0/AD1 EQB1/AD2 EQB0 APRIL2011 REVISEDJANUARY20155 Pin Configurationand FunctionsDS80 PCI80054 LeadTop ViewCopyright 2011 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks:DS80 PCI800DS80 PCI800 SNLS334G APRIL2011 Functions(1)(2)(3)(4)PINI/O, +,INB_0-,Invertingand non-invertingdifferentialinputsto bankB gatedon-chip50- INB_1+,INB_1-,1, 2, 3, 4,terminationresistorconnectsINB_n+to VDDand INB_n-to VDDdependingon the stateI, CMLINB_2+,INB_2-,5, 6, 7, 8of Table4 INB_3+,INB_3-AC couplingrequiredon high-speedI/OINA_0+,INA_0-,Invertingand non-invertingdifferentialinputsto bankA gatedon-chip50- 10, 11, 12,INA_1+,INA_1-,terminationresistorconn ectsINA_n+to VDDand INA_n-to VDDdependingon the state13, 15, 16,I, CMLINA_2+,INA_2-,of Table417, 18 INA_3+,INA_3-AC couplingrequiredon high-speedI/OOUTB_0+,OUTB_0-,45, 44, 43,OUTB_1+,OUTB_1-,Invertingand non-inverting50- driverbankB outputswith , 40, 39,O, CMLOUTB_2+,OUTB_2-,with , 37 OUTB_3+,OUTB_3-OUTA_0+,OUTA_0-,35, 34, 33,OUTA_1+,OUTA_1-,Invertingand non-inverting50- driverbankA outputswith , 31, 30,O, CMLOUTA_2+,OUTA_2-,with , 28 OUTA_3+.

5 OUTA_3-CONTROLPINS SHARED(LVCMOS)Systemmanagementbus (SMBus)enablepinI, 4-LEVEL,Tie 1 k to VDD( )or VIN ( V-mode)= RegisteraccessSMBusslavemodeENSMB48 LVCMOSFLOAT= ReadexternalEEPROM(masterSMBUS mode)Tie 1 k to GND= Pin modeENSMB= 1 (SMBusSLAVEMODE)I, 2-LEVEL,In SMBusSlaveMode,this pin is the SMBusclockI/O. Clockinputor ,SCL50 External2-k to 5-k pullupresistorto VDDor VIN recommendedas per SMBusO, openinterfacestandards.(5)drainI, 2-LEVEL,In bothSMBusModes,this pin is the SMBusdataI/O. Datainputor ,SDA49 External2-k to 5-k pullupresistorto VDDor VIN recommendedas per SMBusO, openinterfacestandards.(5) bothSMBusModes,thesepins are the userset SMBus54, 53, 47,I, 4-LEVEL, pullupor SD_TH26I, FLOATIn SMBusSlaveMode,this pin is not FLOAT(SMBusMASTERMODE)I, 2-LEVEL,ClockoutputwhenloadingEEPROM configuration,revertingto SMBusclockinputwhenLVCMOS,EEPROM load is complete(ALL_DONE= 0).

6 SCL50O, openExternal2-k to 5-k pullupresistorto VDDor VIN recommendedas per SMBusdraininterfacestandards.(5)I, 2-LEVEL,In bothSMBusModes,this pin is the SMBusdataI/O. Datainputor ,SDA49 External2-k to 5-k pullupresistorto VDDor VIN recommendedas per SMBusO, openinterfacestandards.(5) bothSMBusModes,thesepins are the userset SMBus54, 53, 47,I, 4-LEVEL, pullupor logiclow on this pin startsthe load fromthe externalEEPROM(6)I, 2-LEVEL,READ_EN26 OnceEEPROM load is complete(ALL_DONE= 0), this pin doesnot revertto an SD_THinput.(1)LVCMOS inputswithoutthe FLOAT conditionsmustbe drivento a logiclow or high at all timesor operationis not verified.(2)Inputedgerate for LVCMOS/FLOAT inputsmustbe fasterthan50 ns from10%to 90%.(3)For ,VIN pin = V and the VDDfor the 4-levelinputis V.(4)For ,VDDpin = V and the VDDfor the 4-levelinputis V.(5)SCLand SDApins can be tied eitherto V or V, regardlessof whetherthe deviceis operatingin (6)WhenREAD_ENis assertedlow, the deviceattemptsto load EEPROM cannotbe loadedsuccessfully,for exampledue toan invalidor blankhex file, the DS80 PCI800waitsindefinitelyin an unknownstatewhereSMBusaccessis not in this 2011 2015, APRIL2011 REVISEDJANUARY2015 Pin Functions(1)(2)(3)(4)(continued)PINI/O, , 2-Validregisterload statusoutputALL_DONE27 LEVEL,HIGH= ExternalEEPROM load failedor incompleteLVCMOSLOW= ExternalEEPROM load passedENSMB= 0 (PINMODE)EQA[1:0]and EQB[1:0]controlthe levelof equalizationon the pins areactiveonly whenENSMBis deasserted(low).

7 The 8 channelsare organizedinto twoEQA0,EQA1,20, 19, 46,I, 4-LEVEL, is controlledwith the EQA[1:0]pins and bankB is controlledwith theEQB0,EQB147 LVCMOSEQB[1:0] the SMBusregistersprovideindependentcontrolo f EQB[1:0]pins are convertedto SMBUSAD2 [1:0]and DEMB[1:0]controlthe levelof de-emphasisof the are only activewhenENSMBis deasserted(low).The 8 channelsare organizedinto two is controlledwith the DEMA[1:0]pins and bankB is controlledDEMA0,DEMA1,49, 50, 53,I, 4-LEVEL,with the DEMB[1:0] the SMBusregistersprovideDEMB0,DEMB154 LVCMOS independentcontrolof DEMA[1:0]pins are convertedto SMBUSSCL/SDAand DEMB[1:0]pins are convertedto AD0, BOTHPIN ANDSMBUSMODES(LVCMOS)RATE controlpin selectsGEN1,2 and GEN3 1 k to GND= GEN1,2I, 4-LEVEL,RATE21 FLOAT= AUTORateSelectof Gen1/2and Gen3with de-emphasisLVCMOSTie 20 k to GND= GEN3 withoutde-emphasisTied1 k to VDD= RESERVEDThe RXDETpin controlsthe the inputlevel,a 50I, 4-LEVEL,RXDET22 or > 50 k terminationto the powerrail is , FLOATF loat(leavepin open)= NormalOperationControlsthe internalregulatorFLOAT= , LVCMOSTie GND= Figure14I, 4-LEVEL,Controlsthe cableis not presentper , 2-LEVEL, Putspart into low (normaloperation)part is , V to VINVIN24 PowerIn ,leavefloatingPowersupplypins9, 14, 36, ,connectto , , F capacitorto eachVDDpin (outputof LDO)GNDDAPP owerGroundpad (DAP- die attachpad)Copyright 2011 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks.

8 DS80 PCI800DS80 PCI800 SNLS334G APRIL2011 (1)(2)(3)MINMAXUNITS upplyvoltage(VDD- ) (VIN- ) + 3030mAJunctiontemperature125 CLeadtemperaturesoldering(4 s)(4)260 CStoragetemperature,Tstg 40125 C(1)StressesbeyondthoselistedunderAbsolu teMaximumRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingRatings. Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay affectdevicereliability.(2)MaximumNumber sare specifiedfor a junctiontemperaturerangeof 40 C to 125 C. Modelsare validatedto MaximumOperatingVoltagesonly.(3)If Military/Aerospacespecifieddevicesare required,contactthe TexasInstrumentsSalesOffice/Distributors for availabilityandspecifications.(4)For solderingspecifications:See (HBM),per ANSI/ESDA/JEDECJS-001,all pins(1) 3000 ElectrostaticV(ESD)Chargeddevicemodel(CD M),per JEDEC specificationJESD22-C101,all pins(2) 1000 VdischargeMachinemodel(MM),per JEDEC specificationJESD22-A115-A 200(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.

9 (2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a ( ) ( ) 402585 CSMBus(SDA,SCL) to 50 MHz(1)100mVp-p(1)Allowedsupplynoise(mVp- psine wave) 2011 2015, APRIL2011 V supply,500700EQ Enabled,mWVOD= Vp-p,RXDET= 1, PRSNT= 0 VIN = V supply,660900EQ Enabled,mWVOD= Vp-p,RXDET= 1, PRSNT= 0 LVCMOS/ LVTTLDC (PRSNT,READ_ENpins) (PRSNT,READ_ENpins) (PRSNT,READ_ENpins)VOHHigh-leveloutputvo ltageIOH= 4 (ALL_DONEpin)VOLLow-leveloutputvoltageIO L= 4 (ALL_DONEpin)IIHI nputhigh current(PRSNTpin)VIN = V, 1515 ALVCMOS= VInputhigh currentwith internal20150 Aresistors(4 levelinputpin)IILI nputlow current(PRSNTpin)VIN = V, 1515 ALVCMOS= 0 VInputlow currentwith internal 160 40 Aresistors(4-levelinputpin)CMLRECEIVERIN PUTS(IN_n+,IN_n-)RLRX-DIFFRX GHz to GHz 14dBRLRX-CMRX GHz to GHz 8dBZRX-DCRX DC single-endedimpedanceTestedat VDD= V405060 ZRX-DIFF-DCRX DC differentialmodeTestedat VDD= V80100120 impedanceZRX-HIGH-IMP-DC inputcommonmodeVID = 0 to 200 mV,50DC-POSimpedancefor V > 0 ENSMB= 0, RXDET= 0,k VDD= VVRX-DIFF-DCDifferentialRX peak-to-peakTestedat (VID)VRX-SIGNAL-DET-Signaldetectassertle velforSD_TH= float,180 DIFF-PPactivedatasignal0101patternat 8 GbpsmVp-pMeasuredat pinsVRX-IDLE-DET-Signaldetectdeassertlev elforSD_TH= float,110 DIFF-PPelectricalidle0101patternat 8 GbpsmVp-pMeasuredat pinsCopyright 2011 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback7 ProductFolderLinks.

10 DS80 PCI800DS80 PCI800 SNLS334G APRIL2011 (continued)PARAMETERTESTCONDITIONSMINTYP MAXUNITHIGH-SPEEDOUTPUTSVTX-DIFF-PPOutpu tvoltagedifferentialswingDifferentialmea surementwith OUT_n+ OUT_n-,terminatedby 50 to GND,Vp-pAC-Coupled,VID = Vp-p,DEM0= 1, DEM1= 0(1)VTX-DE-TX de-emphasisratioVOD= Vp-p, 0, DEM1= RdBGen 1 & 2 modesonlyVTX-DE-RATIO_6TX de-emphasisratioVOD= Vp-p, 6 DEM0= R, DEM1= RdBGen 1 & 2 modesonlytTX-DJDeterministicJitterVID = 800 mV, PRBS15pattern, ,VOD= V,UIppEQ = 0x00,DE = 0 dB (no inputoroutputtraceloss)tTX-RJRandomJitte rVID = 800 mV, 0101pattern, Gbps, V,ps RMSEQ = 0x00,DE = 0 dB, (no inputoroutputtraceloss)tTX-RISE-FALLTX rise/falltime20%to 80%of differentialoutput3545psvoltage(2)tRF-MI SMATCHTX rise/fallmismatch20%to 80%of (2)RLTX-DIFFTX GHz to 4 GHz 11dBRLTX-CMTX GHz to 4 GHz 8dBZTX-DIFF-DCDC differentialTX impedance100 VTX-CM-AC-PPTX AC peak-peakcommonVOD= Vp-p,100mVp-pmodevoltageDEM0= 1, DEM1= 0(2)ITX-SHORTTX shortcircuitcurrentlimitTotalcurrentthe transmittercan supply20mAwhenshortedto VDDor GNDVTX-CM-DC-Absolutedeltaof DC common(2)100 ACTIVE-IDLE-modevoltageduringL0 andmVDELTA electricalidleVTX-CM-DC-LINE-Absolutedel taof DC common(2)25 DELTA modevoltgaebetweenTX+ andmVTX-tTX-IDLE-DATAMax time to transitiontoVID = Vp-p,8 time to transitionto IDLEVID = Vp-p,8 low-to-highEQ = 0x00(3)200psdifferentialpropagationdelay tLSKLane-to-laneskewT = 25 C, VDD= V25pstPPSKPart-to-partpropagationdelayT = 25 C, VDD= V40psskew(1)In GEN3mode,the outputVODlevelis not will be adjustedautomaticallybasedon the VID outputVODlevelset by DEMA/B[1.]