Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers …

1 dual , 16-Bit, GSPS. RF DAC with Channelizers data sheet ad9172 . FEATURES GENERAL DESCRIPTION. Supports multiband wireless applications The ad9172 is a high performance, dual , 16-bit digital-to- analog 3 bypassable, complex data input channels per RF DAC converter (DAC) that supports DAC sample rates to GSPS. GSPS maximum complex input data rate per input The device features an 8-lane, 15 Gbps JESD204B data input port, channel a high performance, on-chip DAC clock multiplier, and digital 1 independent NCO per input channel signal processing capabilities targeted at single-band and multiband Proprietary, low spurious and distortion design direct to radio frequency (RF) wireless applications. 2-tone intermodulation distortion (IMD) = 83 dBc at The ad9172 features three complex data input channels per RF. GHz, 7 dBFS/tone RF output DAC that are bypassable. Each data input channel includes a Spurious free dynamic range (SFDR) < 80 dBc at GHz, configurable gain stage, an interpolation filter, and a channel 7 dBFS RF output numerically controlled oscillator (NCO) for flexible, multiband Flexible 8-lane, Gbps JESD204B interface frequency planning.

2 The device supports up to a GSPS complex Supports single-band and multiband use cases data rate per input channel and is capable of aggregating multiple Supports 12-bit high density mode for increased data complex input data streams up to a maximum complex data rate throughput of GSPS. Additionally, the ad9172 supports ultrawide Multiple chip synchronization bandwidth modes bypassing the Channelizers to provide Supports JESD204B Subclass 1. maximum data rates of up to GSPS ( with 16-bit resolution). Selectable interpolation filter for a complete set of input and GSPS ( with 12-bit resolution). data rates 1 , 2 , 3 , 4 , 6 , and 8 configurable data channel The ad9172 is available in a 144-ball BGA_ED package. interpolation PRODUCT HIGHLIGHTS. 1 , 2 , 4 , 6 , 8 , and 12 configurable final interpolation 1. Supports single-band and multiband wireless applications Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz with three bypassable complex data input channels per RF.

3 Transmit enable function allows extra power saving and DAC at a maximum complex input data rate of GSPS. downstream circuitry protection One independent NCO per input channel. High performance, low noise PLL clock multiplier 2. Ultrawide bandwidth channel bypass modes supporting up Supports GSPS DAC update rate to 3 GSPS data rates with 16-bit resolution and 4 GSPS. Observation ADC clock driver with selectable divide ratios with 12-bit resolution. Low power 3. Low power dual converter decreases the amount of power W at 12 GSPS, dual channel mode consumption needed in high bandwidth and multichannel 10 mm 10 mm, 144-ball BGA_ED with metal enhanced applications. thermal lid, mm pitch APPLICATIONS. Wireless communications infrastructure Multiband base station radios Microwave/E-band backhaul systems Instrumentation, automatic test equipment (ATE). Radars and jammers Rev. 0 Document Feedback Information furnished by analog devices is believed to be accurate and reliable.

4 However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog devices . Tel: 2017 analog devices , Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support ad9172 data sheet TABLE OF CONTENTS. Features .. 1 Serial Port Options .. 29. Applications .. 1 JESD204B Serial data Interface .. 31. General Description .. 1 JESD204B Overview .. 31. Product Highlights .. 1 Physical Layer .. 34. Revision History .. 2 data Link Layer .. 37. Functional Block Diagram .. 3 Syncing LMFC Signals .. 39. 4 Transport Layer .. 45. DC Specifications .. 4 JESD204B Test Modes.

5 46. Digital Specifications .. 5 JESD204B Error 47. Maximum DAC Sampling Rate Specifications .. 5 Digital Datapath .. 50. Power Supply DC Specifications .. 6 Total Datapath Interpolation .. 50. Serial Port and CMOS Pin Specifications .. 9 Channel Digital Datapath .. 52. Digital Input data Timing Specifications .. 10 Main Digital Datapath .. 55. JESD204B Interface Electrical and Speed Specifications .. 11 Interrupt Request Operation .. 61. Input data Rates and Signal Bandwidth Specifications .. 12 Interrupt Service Routine .. 61. AC 13 Applications Information .. 62. Absolute Maximum 15 Hardware Considerations .. 62. Reflow Profile .. 15 analog Interface Considerations .. 65. Thermal Characteristics .. 15 DAC Input Clock Configurations .. 65. ESD Caution .. 15 Clock Output Driver .. 67. Pin Configuration and Function Descriptions .. 16 analog Outputs .. 67. Typical Performance Characteristics .. 19 Start-Up Sequence.

6 68. Terminology .. 26 Register Summary .. 75. Theory of Operation .. 27 Register Details .. 83. Serial Port Operation .. 29 Outline Dimensions .. 144. data Format .. 29 Ordering Guide .. 144. Serial Port Pin Descriptions .. 29. REVISION HISTORY. 6/2017 Revision 0: Initial Version Rev. 0 | Page 2 of 144. data sheet ad9172 . FUNCTIONAL BLOCK DIAGRAM. CHANNEL 0. GAIN ad9172 . N NCO RAMP. CHANNEL 1. UP/DOWN. GAIN GAIN. N NCO PA PROTECT M NCO DAC 0 DAC0 . CHANNEL 2. GAIN. SERDIN0 . N NCO. SERDES. JESD204B CHANNEL 3. GAIN. SERDIN7 . N NCO RAMP. CHANNEL 4 UP/DOWN. SYNCOUT0 GAIN GAIN. SYNCOUT1 . N NCO PA PROTECT M NCO DAC 1 DAC1 . CHANNEL 5. GAIN. N NCO. CLOCK DISTRIBUTION DAC ALIGN. SYNCHRONIZATION AND CLOCK DIVIDER PLL. LOGIC DETECT 1, 2, 3, 4. CONTROL LOGIC 1, 2, 3. RESET CLOCK CLOCK CLOCK. VREF SPI. RECEIVER DRIVER RECEIVER. ISET. IRQ0. IRQ1. TXEN0. TXEN1. SYSREF . CLKOUT . SCLK. SYSREF+. CLKOUT+. CLKIN+. CS. SDIO.

7 SDO. CLKIN . 15453-001. Figure 1. Rev. 0 | Page 3 of 144. ad9172 data sheet SPECIFICATIONS. DC SPECIFICATIONS. = V, = V, = V, = V, = V, and DAC output full-scale current (IOUTFS) =. 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = 40 C to +118 C. For the typical values, TA = 25 C, which corresponds to TJ = 51 C. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bit ACCURACY. Integral Nonlinearity (INL) 7 LSB. Differential Nonlinearity (DNL) 7 LSB. analog OUTPUTS (DAC0+, DAC0 , DAC1+, DAC1 ). Gain Error ( with Internal ISET Reference) 15 %. Full-Scale Output Current Minimum RSET = 5 k 16 mA. Maximum RSET = 5 k 26 mA. Common-Mode Voltage 0 V. Differential Impedance 100 . DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN ). Differential Input Power RLOAD = 100 differential on-chip Minimum 0 dBm Maximum 6 dBm Differential Input Impedance1 100 . Common-Mode Voltage AC-coupled V.

8 CLOCK OUTPUT DRIVER (CLKOUT+, CLKOUT ). Differential Output Power Minimum 9 dBm Maximum 0 dBm Differential Output Impedance 100 . Common-Mode Voltage AC-coupled V. Output Frequency 3000 MHz TEMPERATURE DRIFT. Gain 10 ppm/ C. REFERENCE. Internal Reference Voltage V. analog SUPPLY VOLTAGES. V. V. DIGITAL SUPPLY VOLTAGES. V. V. V. SERIALIZER/DESERIALIZER (SERDES) SUPPLY VOLTAGES. V. 1. See the DAC Input Clock Configurations section for more details. Rev. 0 | Page 4 of 144. data sheet ad9172 . DIGITAL SPECIFICATIONS. = V, = V, = V, = V, = V, and DAC output full-scale current (IOUTFS) =. 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = 40 C to +118 C. For the typical values, TA = +25 C, which corresponds to TJ = 51 C. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DAC UPDATE RATE. Minimum GSPS. Maximum1 16-bit resolution, with interpolation GSPS. 16-bit resolution, no interpolation GSPS.

9 Adjusted2 16-bit resolution, with interpolation GSPS. 16-bit resolution, no interpolation GSPS. DAC PHASE-LOCKED LOOP (PLL). VOLTAGE CONTROLLED OSCILLATOR. (VCO) FREQUENCY RANGES. VCO Output Divide by 1 GSPS. VCO Output Divide by 2 GSPS. VCO Output Divide by 3 GSPS. PHASE FREQUENCY DETECT INPUT. FREQUENCY RANGES. GHz VCO Frequency 25 225 MHz GHz VCO Frequency < GHz or 25 770 MHz VCO Frequency > GHz DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN ) FREQUENCY RANGES. PLL Off GHz PLL On M divider set to divide by 1 25 770 MHz M divider set to divide by 2 50 1540 MHz M divider set to divide by 3 75 2310 MHz M divider set to divide by 4 100 3080 MHz 1. The maximum DAC update rate varies depending on the selected JESD204B mode and the lane rate for the given configuration used. The maximum DAC rate according to lane rate and voltage supply levels is listed in Table 3. 2. The adjusted DAC update rate is calculated as fDAC, divided by the minimum required interpolation factor for a given mode or the maximum channel data rate for a given mode.

10 Different modes have different maximum DAC update rates, minimum interpolation factors, and maximum channel data rates, as shown in Table 13. MAXIMUM DAC SAMPLING RATE SPECIFICATIONS. = V, = V, = V, = V, = V, and DAC output full-scale current (IOUTFS) =. 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = 40 C to +118 C. For the typical values, TA = 25 C, which corresponds to TJ = 51 C. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit MAXIMUM DAC UPDATE RATE. = V 5%. Lane rate > 11 Gbps GSPS. Lane rate 11 Gbps GSPS. = V Lane rate > 11 Gbps GSPS. Lane rate 11 Gbps1 GSPS. 1. If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of GSPS, as listed in Table 2. Rev. 0 | Page 5 of 144. ad9172 data sheet POWER SUPPLY DC SPECIFICATIONS. = V, = V, = V, = V, = V, and DAC output full-scale current (IOUTFS) =. 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = 40 C to +118 C.