ELECTRONICS INDUSTRIES Generic Requirements for Surface ...

1 IPC-7351 Generic Requirements forSurface Mount Design andLand Pattern StandardDeveloped by the Surface Mount Land Patterns Subcommittee (1-13)of the Printed Board Design Committee (1-10) of IPCU sers of this publication are encouraged to participate in thedevelopment of future :IPC3000 Lakeside Drive, Suite 309 SBannockburn, Illinois60015-1219 Tel 847 847 :IPC-SM-782A withAmendments1&2 ASSOCIATION CONNECTINGELECTRONICS INDUSTRIES Table of .. Hierarchy .. and Land Pattern FamilyStructure .. Classification .. Levels .. Pattern Determination .. and Definitions .. 32 APPLICABLE .. INDUSTRIES Association .. Industry Standards (IPC) .. Electrotechnical Commission .. Electron Device Engineering Council(JEDEC) .. 63 DESIGN Systems .. Tolerancing .. Tolerancing .. Allowances .. Tolerancing .. and Tolerance Analysis .. Producibility .. Land Pattern .. Component Selection .. Substrate Development.

2 Considerations .. for Automated Test .. for SMT .. Constraints .. Sensitive Components .. Environment Considerations .. Rules .. Spacing .. and Double-Sided Board Assembly .. Stand-off Height for Cleaning .. Marks .. Guidelines .. PCB Fabrication Allowances .. Layer Surface Finishes .. Mask Finishes .. Mask Clearances .. Pattern Surface Finishes .. 314 COMPONENT QUALITY Techniques .. and Assembly Test .. Test .. Board Test .. Access .. Philosophy .. Strategy for Bare Boards .. Nodal Access for Assembled Board .. Test Accommodation .. Testing .. Nodal Access .. Nodal Access .. Fixtures Impact .. Board Test Characteristics .. Land Pattern Spacing .. Land Size and Shape .. for Test Parameters .. 356 PRINTED BOARD STRUCTURE Considerations .. Expansion Mismatch .. Material .. Base Materials .. PCB Structures .. PCB Structures .. PCB Technology.

3 Core Structures .. Metal (Metal Core) Structures .. 397 ASSEMBLY CONSIDERATION FOR SURFACEMOUNT TECHNOLOGY (SMT).. Assembly Process Sequence .. Preparation .. Application .. Adhesive .. Paste Application .. Preforms .. Placement .. 41 IPC-7351 February Data Transfer .. Processes .. Soldering .. Phase (VP) Soldering .. Reflow Soldering .. Air/Gas Convection Soldering .. Reflow Soldering .. Reflow Soldering .. Effects .. on Printed BoardMaterial Type .. on Copper Land andConductor Layout .. 448 IPC-7352 DISCRETE Resistors (RESC) .. Construction .. Package Format .. to Soldering .. Capacitors (CAPC) .. Construction .. Package Format .. to Soldering .. (INDC, INDM, INDP) .. Construction .. Package Format .. to Soldering .. Capacitors (CAPT) .. Construction .. Package Format .. to Soldering .. Electrode Face Diodes (DIOMELF,RESMELF) .. Construction.

4 Package Format .. to Soldering .. Construction .. Package Format .. to Soldering .. Construction .. Package Format .. to Soldering .. Construction .. Package Format .. to Soldering .. Construction .. Package Format .. to Soldering .. Basic Construction .. Marking .. Carrier Package Format .. Resistance to Soldering .. (DPAK Type) .. Basic Construction .. Marking .. Carrier Package Format .. Resistance to Soldering .. Body Diode (DIOSMB) .. 499 IPC-7353 GULLWING LEADED COMPONENTS,TWO .. Construction .. Package Format .. to Soldering .. (SSOIC) .. Construction .. Package Format .. to Soldering .. (SOP-IPC-782) .. Package Format .. to Soldering .. Packages Format .. 51 February to Soldering .. Packages Format .. to Soldering .. 5210 IPC-7354 J-LEADED COMPONENTS,TWO Construction .. Package Format .. Considerations .. 5211 IPC-7355 GULL-WING LEADEDCOMPONENTS, FOUR (PQFP).

5 Carrier Package Format .. Carrier Package Format .. Carrier Package Format .. Package Format .. 5412 IPC-7356 J LEADED COMPONENTS,FOUR .. Plastic Chip Carriers .. Plastic Chip Carriers .. Plastic Chip Carriers .. Plastic Chip Carriers .. 5613 IPC-7357 POST (DIP) LEADS, TWO Materials .. Package Format .. to Soldering .. 5614 IPC-7358 AREA ARRAY COMPONENTS(BGA, FBGA, CGA).. Array Configurations .. Packages .. Pitch BGA Package (FBGA) .. Column Grid Arrays (CGA) .. Configuration Issues .. Outlines .. Matrix Options .. Depopulation .. Site Planning .. Contact Assignment .. and Shipping .. Pattern Analysis .. Approximation .. Variation .. Ball Conditions .. Pattern Calculator .. 6215 IPC-7359 NO LEAD COMPONENTS (QFN,SON, LCC).. Package Format .. Considerations .. Flat No-Lead (QFN) .. Package Format .. Considerations .. Resist Considerations .. Outline No-Lead (SON).

6 Package Format .. Considerations .. Resist Considerations .. 6516 ZERO COMPONENT 65 APPENDIX A(Informative) Test Patterns Process 71 APPENDIX B(Informative) Abbreviationsand 73 APPENDIX CIPC-7351 Land Pattern 74 FiguresFigure 3-1 Profile Tolerancing Method .. 6 Figure 3-2 Example of 3216 (1206) CapacitorDimensioning for Optimum Solder FilletCondition .. 7 Figure 3-3 Profile Dimensioning of Gull-WingLeaded SOIC .. 8 Figure 3-4 Pitch for Multiple Leaded Components .. 11 Figure 3-5 Courtyard Boundary Area Condition .. 15 Figure 3-6 Component Orientation for Wave-SolderApplications .. 21 Figure 3-7 Alignment of Similar Components .. 21 Figure 3-8 Panel/Local Fiducials .. 22 Figure 3-9 Local Fiducials .. 23 Figure 3-10 Fiducial Locations on a Printed Board .. 23 Figure 3-11 Fiducial Size and Clearance Requirements .. 24 IPC-7351 February 2005viFigure 3-12 Use of Vias in High Component DensityPrinted Circuit Boards .. 25 Figure 3-13 Conductor Routing Capability Test Pattern.

7 25 Figure 3-14 Land Pattern to Via Relationship .. 26 Figure 3-15 Examples of Via Positioning Concepts .. 26 Figure 3-16 Vias Under Components .. 27 Figure 3-17 Conductor Description .. 28 Figure 3-18 Examples of Modified Landscapes .. 28 Figure 3-19 Typical Copper Glass Laminate Panel .. 29 Figure 3-20 Conductor Clearance for V-Groove Scoring .. 30 Figure 3-21 Breakaway (Routed Pattern) withRouted Slots .. 31 Figure 3-22 Gang Solder Mask Window .. 31 Figure 3-23 Pocket Solder Mask Window .. 31 Figure 4-1 Component Operating Temperature Limits .. 32 Figure 5-1 Test Via Grid Concepts .. 34 Figure 5-2 General Relationship Between TestContact Size and Test Probe Misses .. 35 Figure 5-3 Test Probe Feature Distance fromComponent .. 36 Figure 7-1 Typical Process Flow for Full SurfaceMount Type 1b and 2b Surface MountTechnology .. 40 Figure 7-2 Assembly Process Flow for Two-SideSurface Mount with PIH .. 41 Figure 8-1 Packaging of Discrete Components.

8 44 Figure 8-2 Chip Resistor Construction .. 45 Figure 8-3 Chip Capacitor Construction .. 46 Figure 8-4 Inductor Construction .. 46 Figure 8-5 Tantalum Capacitor Construction .. 46 Figure 8-6 Metal Electrode Face ComponentConstruction .. 47 Figure 8-7 Break-Away Diagram of MELFC omponents .. 47 Figure 8-8 SOT 23 Construction .. 47 Figure 8-9 SOT 89 Construction .. 48 Figure 8-10 SOD 123 Construction .. 48 Figure 8-11 SOT143 Construction .. 48 Figure 8-12 SOT 223 Construction .. 49 Figure 8-13TO252 (DPAK Type) Construction .. 49 Figure 9-1 SOIC Construction .. 50 Figure 9-2 SOP8/SOP63 Construction .. 50 Figure 9-3 SOP127 Construction .. 51 Figure 9-4 TSSOP Construction .. 51 Figure 9-5 CFP127 Construction .. 51 Figure 10-1 SOJ Construction .. 52 Figure 11-1 BQFP Construction .. 53 Figure 11-2 SQFP and QFP Construction .. 53 Figure 11-3 QFPR Construction .. 54 Figure 11-4 CQFP Construction .. 54 Figure 12-1 PLCC Construction .. 55 Figure 12-2 PLCCR Construction.

9 56 Figure 13-1 DIP Construction .. 56 Figure 14-1 Ball Grid Array (BGA) IC Package Example .. 57 Figure 14-2 Example of Plastic BGA PackageConfigurations .. 57 Figure 14-3 Ceramic Column Grid Array (CGA)Package (Cross-Sectional View) .. 58 Figure 14-4 Bottom View of BGA Devices .. 59 Figure 14-5 One Package Size, Two Full Matrices .. 59 Figure 14-6 Perimeter and Thermally EnhancedMatrices .. 60 Figure 14-7 Staggered Matrix .. 60 Figure 14-8 Selective Depopulation .. 60 Figure 14-9 Device Orientation and Contact A1 Position .. 61 Figure 15-1 Quad Flat No-Lead (QFN) Construction .. 63 Figure 15-2 Quad Flat No-Lead (QFN) Construction(Cross-Sectional View) .. 64 Figure 15-3 Small Outline No-Lead (SON) Construction .. 64 Figure 16-1 Zero Component Rotations for CommonPackage Outlines .. 66 Figure A-1 General Description of Process ValidationContact Pattern and Interconnect .. 71 Figure A-2 Photoimage of IPC-A-49 Test Board forPrimary Side .. 72 TablesTable 3-1 Tolerance Analysis Elements for ChipDevices.

10 11 Table 3-2 Flat Ribbon L and Gull-Wing Leads(greater than mm pitch) (unit: mm) .. 12 Table 3-3 Flat Ribbon L and Gull-Wing Leads (lessthan or equal to mm pitch) (unit: mm) .. 12 Table 3-4J Leads (unit: mm) .. 13 Table 3-5 Rectangular or Square-End Components(Capacitors and Resistors) Equal to or Largerthan 1608 (0603) (unit: mm) .. 13 Table 3-6 Rectangular or Square-End Components(Capacitors and Resistors) Smaller than1608 (0603) (unit: mm) .. 13 Table 3-7 Cylindrical End Cap Terminations (MELF)(unit: mm) .. 13 Table 3-8 Bottom Only Terminations (unit: mm) .. 13 Table 3-9 Leadless Chip Carrier with CastellatedTerminations (unit: mm) .. 13 Table 3-10 Butt Joints (unit: mm) .. 14 Table 3-11 Inward Flat Ribbon L and Gull-Wing Leads(Tantalum Capacitors) (unit: mm) .. 14 Table 3-12 Flat Lug Leads (unit: mm) .. 14 Table 3-13 Flat, No Lead (unit: mm) .. 14 Table 3-14 Small Outline (SO), No-Lead (unit: mm) .. 14 Table 3-15 IPC-7351 Land Pattern Naming Convention.