ESP32-S2 Family - Espressif

1 ESP32-S2 FamilyDatasheetIncluding: ESP32-S2 esp32 -S2FH2 esp32 -S2FH4 esp32 -S2FN4R2 esp32 -S2R2 Version SystemsCopyright This DocumentThis document provides the specifications of ESP32-S2 UpdatesPlease always refer to the latest version HistoryFor any changes to this document over time, please refer to thelast Change NotificationEspressif provides email notifications to keep customers updated on changes to technical subscribe Note that you need to update your subscription to receivenotifications of new products you are not currently subscribed certificates for Espressif products Systems2 Submit Documentation FeedbackESP32-S2 Family Datasheet OverviewESP32-S2 Family is a highly-integrated, low-power.

2 Wi-Fi System-on-Chip (SoC) solution. With itsstate-of-the-art power and RF performance, this SoCis an ideal choice for a wide variety of applicationscenarios relating to Internet of Things (IoT), wearableelectronics and smart Family includes a Wi-Fi subsystem thatintegrates a Wi-Fi MAC, Wi-Fi radio and baseband, RFswitch, RF balun, power amplifier, low noise amplifier(LNA), etc. The chip is fully compliant with the protocol and offers a complete the core of this chip is an Xtensa 32-bit LX7 CPUthat operates at up to 240 MHz. The chip supportsapplication development, without the need for a on-chip memory includes 320 KB SRAM and 128KB ROM. It also supports multiple externalSPI/QSPI/OSPI flash and external RAM chips for morememory Family is designed for ultra-low-powerapplications with its multiple low-power modes.

3 Itsfeatured fine-grained clock gating, dynamic voltageand frequency scaling, and adjustable power amplifieroutput power, contribute to an optimal trade-offbetween communication range, data rate and device provides a rich set of peripheral interfacesincluding SPI, I2S, UART, I2C, LED_PWM, LCDinterface, camera interface, ADC, DAC, touch sensor,temperature sensor, as well as 43 GPIOs. It alsoincludes a full-speed USB On-The-Go (OTG) interfaceto enable USB Family has several dedicated hardwaresecurity features. Cryptographic accelerators areintegrated for AES, SHA and RSA hardware security features are provided bythe RNG, HMAC and Digital Signature modules as wellas flash encryption and secure boot signatureverification features.

4 These features allow the device tomeet stringent security DiagramCryptographic Hardware AccelerationRTCWi-FiMain CPUJTAGULP co-processorRTC memoryPMUWi-Fi MAC Wi-Fi basebandXtensa 32-bit LX7 MicroprocessorROMC acheSRAMP eripherals and SensorsRFRF receiverRF transmitterClock generatorSHARSAAESRNGS witchBalunEspressif s ESP32-S2 Wi-Fi SoCHMACD igital signatureSPI / LCD interfaceI2CI2S / Camera interface / LCD interfaceUARTRMTLED_PWMT emperature sensorDACADCUSB OTGT ouch sensorGPIOP ulse counterGeneral purpose TimersEmbedded flash / PSRAMTWAIF igure 1: Block Diagram of ESP32-S2 Espressif Systems3 Submit Documentation FeedbackESP32-S2 Family Datasheet IEEE b/g/n-compliant Supports 20 MHz, 40 MHz bandwidth in band Single-band 1T1R mode with data rate up to150 Mbps WMM TX/RX A-MPDU, RX A-MSDU Immediate Block ACK Fragmentation and defragmentation Automatic Beacon monitoring (hardware TSF) 4 virtual Wi-Fi interfaces Simultaneous support for Infrastructure Station,SoftAP, and Promiscuous modesNote that when ESP32-S2 Family is in Stationmode and performs a scan, the SoftAP channelwill change along with the Station channel.

5 Antenna diversity FTMCPU and Memory Xtensa single-core 32-bit LX7 microprocessor,up to 240 MHz 128 KB ROM 320 KB SRAM 16 KB SRAM in RTC Embedded flash and PSRAM (see details inChapter1: Family Member Comparison) SPI/QSPI/OSPI supports multiple flash andexternal RAM chipsAdvanced Peripheral Interfaces 43 programmable GPIOs 2 13-bit SAR ADCs, up to 20 channels 2 8-bit DAC 14 touch sensing IOs 4 SPI 1 I2S 2 I2C 2 UART RMT (TX/RX) LED PWM controller , up to 8 channels 1 full-speed USB OTG 1 temperature sensor 1 DVP 8/16 camera interface, implementedusing the hardware resources of I2S 1 LCD interface (8-bit serial RGB/8080/6800),implemented using the hardware resources ofSPI2 1 LCD interface (8/16/24-bit parallel),implemented using the hardware resources ofI2S 1 TWAI controller compatible with ISO11898-1 (CAN Specification )

6 Security Secure boot Flash encryption 4096-bit OTP, up to 1792 bits for users Cryptographic hardware acceleration: AES-128/192/256 (FIPS PUB 197) Hash (FIPS PUB 180-4) Espressif Systems4 Submit Documentation FeedbackESP32-S2 Family Datasheet RSA Random Number Generator (RNG) HMAC Digital signatureApplications (A Non-exhaustive List) Generic Low-power IoT Sensor Hubs Generic Low-power IoT Data Loggers Cameras for Video Streaming Over-the-top (OTT) Devices USB Devices Speech Recognition Image Recognition Mesh Networks Home Automation Light control Smart plugs Smart door locks Smart Buildings Smart lighting Energy monitoring Industrial Automation Industrial wireless control Industrial robotics Smart Agriculture Smart greenhouses Smart irrigation Agriculture robotics Audio Applications Internet music players Live streaming devices Internet radio players Audio headsets Health Care Applications Health monitoring Baby monitors Wi-Fi-enabled Toys remote control toys Proximity sensing toys Educational toys Wearable Electronics Smart watches Smart bracelets Retail & Catering Applications POS machines Service robots touch Sensing

7 Applications Waterproof design Distance sensing applications Linear slider, wheel slider designsEspressif Systems5 Submit Documentation FeedbackESP32-S2 Family Datasheet Overview3 Block Diagram3 Features4 Applications51 Family Member Family Comparison102 Pin Pin Pin Power Strapping Pins163 Functional CPU and Internal External Flash and Address Mapping System CPU RTC Audio PLL Analog Analog-to-Digital Converter (ADC) Digital-to-Analog Converter (DAC) Temperature touch Digital General Purpose Input / Output Interface (GPIO) Serial Peripheral Interface (SPI) LCD Universal Asynchronous Receiver Transmitter (UART) I2C I2S Camera Infrared remote Pulse LED PWM USB OTG25 Espressif Systems6 Submit Documentation FeedbackESP32-S2 Family Datasheet TWAI Radio and GHz GHz Clock Wi-Fi Radio and Wi-Fi Networking RTC and Low-Power Power Management Unit (PMU) Ultra-Low-Power Timers and 64-bit Watchdog Cryptographic Hardware Physical Security Peripheral Pin Configurations304 Electrical Absolute Maximum Recommended Operating VDD_SPI Output DC Characteristics ( V, 25 C)

8 ADC Current Consumption Reliability Wi-Fi Transmitter Receiver Characteristics385 Package Information406 Learning Must-Read Must-Have Resources41 Appendix A ESP32-S2 Pin IO GPIO Matrix43 Revision History48 Espressif Systems7 Submit Documentation FeedbackESP32-S2 Family Datasheet of Tables1 ESP32-S2 Family Member Comparison102 Pin Description123 Description of ESP32-S2 Family Power-up and Reset Timing Parameters164 Strapping Pins165 Capacitive-Sensing GPIOs Available on ESP32-S2 Family216 Peripheral Pin Configurations307 Absolute Maximum Ratings348 Recommended Operating Conditions349 VDD_SPI Output Characteristics3410 DC Characteristics ( V, 25 C)3511 ADC Characteristics3512 Current Consumption Depending on RF Modes3613 Current Consumption Depending on Work Modes3614 Reliability Qualifications3715 Transmitter Characteristics3816 Receiver Characteristics3817 GPIO_Matrix43 Espressif Systems8 Submit Documentation FeedbackESP32-S2 Family Datasheet of Figures1 Block Diagram of esp32 -S232 ESP32-S2 Family Nomenclature103 ESP32-S2 Pin Layout (Top View)114 ESP32-S2 Family Power Scheme155 ESP32-S2 Family Power-up and Reset Timing166 Address Mapping Structure197 QFN56 (7 7 mm)

9 Package40 Espressif Systems9 Submit Documentation FeedbackESP32-S2 Family Datasheet Family Member Member NomenclatureESP32-S2 FxChip familyEmbedded flashFlash size (MB)RxEmbedded PSRAMPSRAM size (MB)H 1 Flash temperatureH: High temperatureN: Normal temperatureFigure 2: ESP32-S2 Family 1: ESP32-S2 Family Member ComparisonOrdering CodeEmbedded FlashEmbedded PSRAMA mbient Temperature ( C) ESP32-S2 40 105 esp32 -S2FH22 MB 40 105 esp32 -S2FH44 MB 40 105 esp32 -S2FN4R24 MB2 MB 40 85 esp32 -S2R2 2 MB 40 85 Note:For junction temperature, please refer to Systems10 Submit Documentation FeedbackESP32-S2 Family Datasheet Pin Layout1234567892930313233343536373839404 1421516171819202122232425262845464748495 05152535455564443 ESP32-S2 Family1314101112 VDD3P3_RTC_IO27 GPIO21 GPIO20 GPIO19 DAC_2 DAC_1 XTAL_32K_NXTAL_32K_PVDD3P3_RTCGPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 VDD3P3 VDD3P3 LNA_INVDDACHIP_PUVDDAXTAL_PXTAL_NVDDAGPI O45U0 RXDU0 TXDMTMSMTDIVDD3P3_CPUMTD0 MTCKGPIO46 GPIO38 GPIO37 GPIO36 GPIO35 GPIO34 GPIO33 SPIDSPIQSPICLKSPICS0 SPIWPSPIHDVDD_SPISPICS157 GNDF igure 3.

10 ESP32-S2 Pin Layout (Top View) Espressif Systems11 Submit Documentation FeedbackESP32-S2 Family Datasheet Pin DescriptionTable 2: Pin domainFunctionVDDA1PA Analog power supplyLNA_IN2I/O RF input and outputVDD3P33PA Analog power supplyVDD3P34PA Analog power supplyGPIO05I/O/TVDD3P3_RTC_IORTC_GPIO0, GPIO0 GPIO16I/O/TVDD3P3_RTC_IORTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 GPIO27I/O/TVDD3P3_RTC_IORTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 GPIO38I/O/TVDD3P3_RTC_IORTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 GPIO49I/O/TVDD3P3_RTC_IORTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 GPIO510I/O/TVDD3P3_RTC_IORTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 GPIO611I/O/TVDD3P3_RTC_IORTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 GPIO712I/O/TVDD3P3_RTC_IORTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 GPIO813I/O/TVDD3P3_RTC_IORTC_GPIO8, GPIO8, TOUCH8.