Examples of communication interfaces

1 1 Examples ofcommunication interfacesTranditional interfaces No intelligence in the interface Only physical connectionOnly physical connectionThis could include changes in voltage levels and transformation from ballanced to unballanced signal We define the communication protocol in ourapplication programWe might use preprogrammed modules for this We have full control of the channel and can usethe interface for our own communication protocolsif we like2 Modern interfaces A high level of intelligence in the interface The communication protocol is defined in theinterface Much of the control of the communicationchannel is left to the interface and we haveto follow the rules of the communicationstandard to be able to communicateHere we will focus on the older type of interfaces3 Parallel linkUnit 1 Unit 2 Serial linkUnit 1 Unit 24 Skew in parallel linkRisk of missreadingUnbalanced linkOne signal lineTransmitterReciverGround5 Balanced linkPiti liTransmitterReciverPositive lineNegative lineNo ground besides maybe shieldingDisturbance on a unbalanced linkThe level refered to ground changesCould give missread signal6 Disturbance on a balanced linkBoth levels change in the same way so the difference is the sameLower risk for missread signalModemModulator/demodulatorTelefon modemsTe l e f o n modemsExample one direction 1 980 Hz 0 1180 HzIn the other direction 1 1650 Hz 0 1850 Hz7 Parallel interfacesTwo Examples memory interface GPIBM emory interfaceExample from HC12 Two emulation modes Emulation expanded wide 16 bit address bus 16 bit data busPORTA and PORTBPORTA

2 And PORTBM ultiplexing Emulation expanded narrow 16 bit address bus 8 bit data busPORTA and PORTBPORTAM ultiplexing8 memory interface 8K static RAM, 6264 13 Address lines 8K addresses 13 Address lines 8K addresses 8 Data lines byte oriented Output enable /OE active lowOpen for reading Write enable /WE active lowOpen for writing Two chip select signals CS1 and CS2 Activate chipMemory interface phases Address phase Data phaseThe memory chip still needs to be addressedduring the data phasedu ge da a p aseControl using external logic9 memory interface signals from the processor Read/write R/W E clock ECLKHigh for readLow for writeLow during address phaseHigh during data phaseMemory interface decodingBddC000 Base address C000A15 A13 = 110131415131415 AAAAAACS1 10 memory interface for Write Enable /WE Active (low) in data phase (ECLK high)Active (low) in data phase (ECLK high)

3 And when R/W is lowECLKR/W/WE001011100111R/WECLKWE memory interface for Output Enable /OE Active (low) in data phase (ECLK high)Active (low) in data phase (ECLK high)and when R/W is highECLKR/W/OE001011101110R/WECLKOE 11 memory interface logicMemory interface be used for more than one memory area12 GPIBP arallel bus for measurement instrumentsGeneral Purpose Instrument Bus IEEE-488 of Electrical and Electronics EngineersInternational Electrotechnical Commision SCPIS tandard Commands for Programmable InstrumentsGPIB to 15 instrumentsThree types of devices Controller Ta l k e r ListenerOne instrument can have more than one function13 GPIB GPIB up Mbyte/secondHigh speed GPIB HS488 up togpp8 Mbyte/secondGPIB data lines8 ground lines3 handshake lines5 interface management lines14 GPIB handshake linesNRFD Not Ready for DataNDAC Not Data AcceptedDAV Data ValidGPIB interface management linesATN AttentionEOI End or IdentifyIFC interface

4 ClearREN Remote EnableSRQ Service Request15 GPIB configurationLinearLinear16 GPIB configuration 1 Device 2 Device 4 Device 3 GPIB configuration linear and starCombined linear and starDevice 1 Device 2 Device 5 Device 4 Device 3 Device 617 GPIB one ~ -12 VoltsLogic zero ~ +12 VoltsSynchroniousor asynchroniousUp to 20 Kbps in standard but used for higher bit rates, for example 115,2 KbpsDistances up to 15 meter18RS-232-C signals 25 pin DSUBRS-232-C signals 9 pin DSUBSCI Asynchronous communication Interface19 Connecting a DTE unit to a DTE unitDTE1 DTE2 Pin Abbriviation PinAbbriviation1 DCD1 DCD2RD 3 TD3TD 2 RD4 DTR 6 DSR5SG 5 SG6 DSR 4 DTR7 RTS8 CTS8 CTS7 RTS9 RIRIZero modemPinOutputPinInput4 DTR 1 DCD6 DSR7 RTS8 CTS20 Simplified connectionSometimes only Rx and Tx are implementedThis could be donestraightIn this case the RD and TD connections must be reversed in one most cases at the DCER eversed functionDTEDCER eversed functionSimplified connectionSometimes only Rx and Tx are implementedThis could also be donecrossed-overThis type of connection is necessary when two master units are connected togetherMake sure that you use the correct type of cable21

5 Transfer of the letter A (6510=4116) odd parityOdd number of onesStart with LSBIdleStartbit1000 0001 StopbitData+12V+5 VParitybit+12V-12 VRS-232 Transfer of the letter A even parityEven number of onesStStPtartbittopbitaritybit22 Transfer of the letter A space parityAlSSPA lways zeroStartbitStopbitParitybitTransfer of the letter A mark parityAlways oneStartStopParittbitpbittybit23 Transfer of the letter A no parityNitbitIdle1000 0001 Data+5 VNo parity bitTypical asynchronoustransmitterTransmission interrupt request transactionData shifted outParallel transfer24 Typical asynchronousreceiverReception interrupt request transactionDt hiftdiData shifted inParallel transferBaud rate and symbol rateBaud rate is the number of signal changes per secondSymbol rate is the number of symbols per secondIn simple transmission the two

6 Are the sameIn modern transmission techniques (modulation) more thanone symbol can be sent in each bit so the symbol rate might be higher than the baud rate25 Hamming codingExample4 data bits3 parity bitsD3D2D1P2D0P1P0 Hamming coding of parity bits 012002311232 DDDPDDDPDDDP exclusive-OR26 Hamming coding of status bits 21232 PDDDS 001201023121232 PDDDSPDDDSPDDDSS2S1S0give error positionPosition 7 MSB (to the left)Position 1 LSB (to the right)Hamming coding are to transmit the data sequence10110123 DDDDWe get the control bits 0101010102311232 DDDPDDDP 01100120 DDDPWe send the total sequence10101000102123 PPDPDDD27 Hamming coding the receiver we decode the check bits 001100010100101001201023121232 PDDDSPDDDSPDDDSThe resultindicates that the transfer is correct000012 SSSH amming coding that there is a transmission error in bit D1and we receive the incorrect sequence10001000102123 PPDPDDDWe decode the check bits 1010000101100011023121232 PDDDSPDDDSPDDDS 1010000120 PDDDS100125101 SSSindicates an error in bit 5 counted from the right, that is in D1We can indicate and correct errors in both data and parity bitsbut only one bit error28RS-422, RS-423 and RS-485RS-423 unbalanced.

7 Faster than RS-232but signal compatible half duplexbut signal compatible, half duplexRS-422 balanced version of RS-423, half duplexRS-485, balanced, multi masterReturn to zero protocols 1 high duty rate 0 low duty rateSynchronisation29 Return to zero protocols cont. 0 negative pulse 1 positive pulseSynchronisationSerial peripheral interface , SPIS ynchroniousSeparate clock lineSeparate transfer lines in the two directionsMaster and slave(s)Separate clock lineBit rate up to tens of MbpsPeripherals at short distance30 Serial peripheral interface , SPIone slaveFrom master to slaveFrom slave to masterMasterSlavereSerial clockSlave selectSerial peripheral interface , SPI31 Serial peripheral interface , SPImultiple slavesSMasterSlave 2lave 1 Slave 3 Separate Slave selectsSerial peripheral interface , SPIclocking conditions32 Serial peripheral interface , SPIclocking conditions peripheral interface , SPIclocking conditions bitSample bitMOSIMISOSS33 Inter-integrated circuit, I2 CSynchroniousyBus topologyBit rates up to MbpsInter-integrated circuit, I2 CPull up34 Inter-integrated circuit, I2C circuit.

8 I2C transmitting two bytes of data to slaveSSlave addressADataADataR/WA/AP 0' writeFrom master to slaveFrom slave to masterR/W = read/writeA = acknowledgeS = start conditionP = stop conditionA = not acknowledgeg35 Inter-integrated circuit, I2C receiving two bytes of data from slaveInter-integrated circuit, I2C condition36 Inter-integrated circuit, I2C conditionInter-integrated circuit, I2C condition37 Inter-integrated circuit, I2C conditionInter-integrated circuit, I2C transactionSDASCLBit transactionData valid381-wire busDallas SemiconductorBus and ground Bus interfaceTwisted pair One master and slavesPower supply through the bus1-wire busStructurePull up391-wire busSignalingBhihhidlBus high when idleReset (from master)Bus low more than 480 seconds1-wire busBit transferStart of bit transferMaster pulls bus low for a short whileSending node (master or slave) 1 keeps the bus low for more than 60 secondsStart of bit transfer1 keeps the bus low for more than 60 seconds 0 keeps the bus low for less than 15 secondsBits are transmitted LSB first401-wire busEach device has a unique serial number64 bits8 bits family code identify the device type48 bits unique device code8 CRC check sum1-wire busPower to slave through the bus411-wire busPower to slave through the bus charged when bus is highCapacitor charged when bus is highCapacitor isolated from bus when bus is lowCapacitor supplies the power