先进先出队列(FIFO HS) - cdn.gowinsemi.com.cn

1 Gowin ( fifo HS) ,2021-07-01 2021 Gowin GowinSynthesis , 2021/01/15 2021/02/04 4 2021/07/01 4 fifo SC HS IP 5 fifo HS IP i .. i.

2 Iii .. v 1 .. 1 .. 1 .. 1 .. 1 .. 2 2 fifo .. 3 fifo .. 3 fifo HS/ fifo SC HS IP .. 4 fifo HS/ fifo SC HS IP .. 5 fifo HS IP .. 5 fifo SC HS IP .. 6 fifo HS IP .. 6 fifo SC HS IP .. 8 3 .. 10 fifo HS IP .. 10 fifo SC HS IP .. 11 4 .. 12 fifo HS IP .. 12 fifo SC HS IP .. 19 5 fifo HS/ fifo SC HS IP .. 26 fifo HS IP .. 26 fifo SC HS IP .. 30 ii 6 .. 34 iii 2-1 fifo HS IP .. 4 2-2 fifo SC HS IP .. 4 4-1 fifo HS .. 12 4-2 fifo HS IP .. 13 4-3 fifo HS.

3 13 4-4 fifo HS IP .. 14 4-5 fifo HS .. 14 4-6 fifo HS IP .. 15 4-7 fifo HS .. 15 4-8 fifo HS IP .. 16 4-9 fifo HS .. 17 4-10 fifo HS IP .. 17 4-11 fifo HS .. 18 4-12 fifo HS IP .. 18 4-13 fifo SC HS .. 19 4-14 fifo SC HS IP .. 19 4-15 fifo SC HS .. 20 4-16 fifo SC HS IP .. 20 4-17 fifo SC HS .. 21 4-18 fifo SC HS IP .. 21 4-19 fifo SC HS .. 22 4-20 fifo SC HS IP .. 23 4-21 fifo SC HS .. 23 4-22 fifo SC HS IP .. 24 4-23 fifo SC HS .. 24 4-24 fifo SC HS IP .. 25 iv 5-1 fifo HS IP .. 26 5-2 FIFO_SC HS IP .. 30 v 1-1.

4 1 2-1 fifo HS/ fifo SC HS IP .. 5 2-2 fifo HS IP .. 7 2-3 fifo HS IP .. 8 2-4 fifo SC HS IP .. 9 2-5 fifo SC HS IP .. 9 3-1 fifo HS IP IO .. 10 3-2 fifo SC HS IP IO .. 11 5-1 fifo HS IP .. 27 5-2 fifo SC HS IP .. 31 1 1(34) 1 fifo HS Gowin fifo HS IP DS100 GW1N FPGA DS117 GW1NR FPGA DS821 GW1NS FPGA DS861 GW1 NSR FPGA DS841 GW1NZ FPGA DS102 GW2A FPGA DS226 GW2AR FPGA 1-1 1-1 fifo First Input First Output IP Intellectual Property RAM Random Access Memory LUT Look-up Tables GSR Global System Reset ECC Error Correcting Code 1 2(34)

5 E-mail Tel +86 755 8262 03912 fifo fifo 3(34) 2 fifo fifo fifo First In First Out fifo fifo fifo fifo fifo fifo fifo fifo fifo fifo fifo fifo fifo fifo HS fifo fifo SC HS IP fifo ( fifo HS IP) 2-1 2-2 2 fifo fifo HS/ fifo SC HS IP 4(34) 2-1 fifo HS IP / / / 2-2 fifo SC HS IP / / / fifo HS/ fifo SC HS IP Gowin fifo IP fifo fifo SC HS IP fifo ( fifo HS) IP fifo fifo 2 fifo fifo HS/ fifo SC HS IP 5(34) Gowin IP Core Generator fifo IP fifo IP 2-1 fifo HS/ fifo SC HS IP fifo HS IP fifo SC HS ip ip Verilog (encrypted)

6 GowinSynthesis Gowin Software ( ) fifo HS/ fifo SC HS IP fifo HS IP Gowin fifo HS IP fifo HS IP Block SRAM Shadow SRAM LUT 2n 65536 1-256 bit 2n 65536 = x / GSR fifo IP 2 fifo fifo HS IP 6(34)

7 ECC fifo HS IP Block SRAM 64bit ECC RdEn RdEn First-Word Fall-Through fifo SC HS IP GOWIN fifo SC HS IP fifo SC HS IP Block SRAM Shadow SRAM LUT 2n 65536 1-256 bit ECC fifo SC HS Block SRAM 64bit ECC RdEn RdEn First-Word Fall-Through fifo HS IP Gowin fifo Verilog fifo HS IP fifo HS IP 2-2 2-3 2 fifo fifo HS IP 7(34) BSRAM fifo Type Block SRAM fifo Type 2-2 fifo HS IP fifo Type Depth x Width FPGA Series Performance (MHz)

8 Reg LUT ALU Logics BSRAM Block SRAM 4096 x 16 GW2A-55-484 WrClk= 54 35 39 74 4 512 x 16 WrClk= RdClk= 42 27 30 57 1 64 x 16 WrClk= RdClk= 30 19 21 40 1 4096 x 16 GW2A-18-484 WrClk= RdClk= 54 35 39 74 4 512 x 16 WrClk= RdClk= 42 27 30 57 1 64 x 16 WrClk= RdClk= 30 19 21 40 1 4096 x 16 GW1N-4-144 WrClk= RdClk= 54 35 39 74 4 512 x 16 WrClk= RdClk= 42 27 30 57 1 64 x 16 WrClk= RdClk= 30 19 21 40 1 2 fifo fifo SC HS IP 8(34) 2-3 fifo HS IP fifo Type Depth x Width FPGA Series Performance (MHz) Reg LUT ALU Logics BSRAM Data NUM Flag con ECC BSRAM 4096 x 16 GW2A-55-484 WrClk= RdClk= 162 141 82 223 4 Yes Yes Yes 512 x 16 WrClk= RdClk= 126 122 64 186 1 Yes Yes Yes 64 x 16 WrClk= RdClk= 90 110 46 156 1 Yes Yes Yes 4096 x 16 GW2A-18-484 WrClk= RdClk= 162 141 82 223 4 Yes Yes Yes 512 x 16 WrClk= RdClk= 126 122 64 186 1 Yes Yes Yes 64 x 16 WrClk= RdClk= 90 110 46 156 1 Yes Yes Yes 4096 x 16 GW1N-4-144 WrClk= RdClk= 162 141 82 223 4 Yes Yes Yes 512 x 16 WrClk= RdClk= 126 122 64 186 1 Yes Yes Yes 64 x 16 WrClk= RdClk= 90 110 46 156 1 Yes Yes Yes fifo FPGA fifo SC HS IP

9 Gowin fifo Verilog fifo SC HS fifo SC HS IP 2-4 2-5 BSRAM fifo Type Block SRAM fifo Type 2 fifo fifo SC HS IP 9(34) 2-4 fifo SC HS IP fifo Type Depth x Width FPGA Series Performance (MHz) (MHz) Reg LUT ALU Logics BSRAM Block SRAM 4096 x 16 GW2A-55-484 54 13 65 78 4 512 x 16 42 11 50 61 1 64 x 16 30 9 35 44 1 4096 x 16 GW2A-18-484 54 13 65 78 4 512 x 16 42 11 50 61 1 64 x 16 30 9 35 44 1 4096 x 16 GW1N-4-144 54 13 65 78 4 512 x 16 42 11 50 61 1 64 x 16 30 9 35 44 1 2-5 fifo SC HS IP fifo Type Depth x Width FPGA Series Performance (MHz) (MHz)

10 Reg LUT ALU Logics BSRAM Data NUM Flag con ECC BSRAM 4096 x 16 GW2A-55-484 71 110 83 193 4 Yes Yes Yes 512 x 16 56 105 65 170 1 Yes Yes Yes 64 x 16 41 102 47 149 1 Yes Yes Yes 4096 x 16 GW2A-18-484 71 110 83 193 4 Yes Yes Yes 512 x 16 56 105 65 170 1 Yes Yes Yes 64 x 16 41 102 47 149 1 Yes Yes Yes 4096 x 16 GW1N-4-144 69 19 78 97 4 Yes Yes Yes 512 x 16 54 16 60 76 1 Yes Yes Yes 64 x 16 39 12 42 54 1 Yes Yes Yes fifo SC HS IP FPGA 3 fifo HS IP 10(34) 3 fifo HS IP fifo HS IP IO 3-1 3-1 fifo HS IP IO Data [WDSIZE-1:0] - WrClk 1 - RdClk 1 - WrEn 1 - RdEn 1 - Reset 1 - WrReset 1 - RdReset 1 - AlmostEmptySetTh [RASIZE-1:0] - 1 AlmostEmptyClrTh [RASIZE-1:0] - 0 AlmostEmptyTh [RASIZE-1:0] - 1 AlmostFullSetTh [ASIZE-1:0] - 1 AlmostFullClrTh [ASIZE-1:0] - 0 AlmostFullTh [ASIZE-1:0] - 1 Q [RDSIZE-1:0] - Empty 1 1 Full 1 0 Wnum [ASIZE: 0] 0 Rnum [RASIZE.]