Hi3518E 1080p/720p IP Camera SoC - Unifore Security

1 Hi3518E 720p IP-Cam SOC. Hi3518E . Key Specifications Processor Core ISP Peripheral Interfaces 440 MHz, 16 KB I-cache, AE and AWB for adjustment POR and externalreset and 16 KB D-cache Highlight compensation, backlight One integrated high-precision RTC. compensation, gamma correction, and One integrated low-speed ADC with dual Video Encoding Protocols color enhancement channels main profile Defect pixel correction, denoising, and Three UART interfaces baseline profile digital image stabilizer One IR interface, one I2C interface, one MJPEG/JPEG baselineencoding ISP tuning tools for PCs SPI master/slave interface, multiple GPIO. interfaces Video Encoding Performance Audio Encoding/Decoding One SDIO interface, supporting SDHC. 2-megapixel maximum resolution for Voice encoding/decoding in compliance Maximum four PWMinterfaces encoding with multiple protocols by using software One USB host port Maximum real-time encoding , ADPCM, and protocols RMII and MII modes.

2 10/100 Mbit/s full- performance of streams: Echo cancellation duplex or half-duplex mode, PHY clock 720p@25 fps+720p@3 fps JPEG snapshot output Multi-stream encoding Security Engine External Memory Interfaces Bit rate control in CBR, VBR, or ABR Various encryption and decryption mode, bit rate ranging from 16 kbit/s to algorithms using hardware, such as AES, SPI NOR flash interface 20 Mbit/s DES, and 3 DES 1-, 2-, or 4-bit SPI NOR flash Encoding of eight ROIs Digital watermark Booting from the NOR flash OSD overlay of eight regions before Video Interfaces SDK. encoding Input SDK based on Integrated Memory 8-, 10-, or 12-bit RGB bayer inputs, High-performance PC decoding Integrated 16-bit DDR2 a maximum of MHz clock library Maximum capacity of 512 Mbits frequency and Physical Specifications Intelligent Video Analysis Compatibility with mainstream HD Power consumption Integrated IVE, supporting various CMOS sensors provided by SONY, Typical power consumption of 900 mW.

3 Intelligent analysis applications such as Aptina, OV, and Panasonic Multi-level power-savingmode motion detection, boundary Security , and Compatibility with CCD sensors Operating voltages video diagnosis Various sensor levels supported V core voltage Programmable sensor clockoutput V I/O voltage, and V margin Video and Graphics Processing Video inputs at 1080p@30 fps or voltage Video pre-processing, including 3D 720p@30 fps V voltage of the internal SDRAM. denoising, image enhancement, edge Output Operating temperature ranging from enhancement, and deinterlacing One VO interface for 0 C (32 F) to +70 C (158 F). Anti-flicker for output videos and graphics connecting to the external HDMI Package 1/16x to 8x video scaling or SDI, maximum performance of RoHS, BGA220.

4 1/2x to 2x graphics scaling 1080p@30 fps Ball pitch of mm ( in.) and OSD overlay pre-processing for eight body size of 11 mm x 11 mm ( in.. Audio Interfaces x in.). regions Hardware graphics overlay post- Integrated audio CODEC, supporting 16- processing for the videos at two layers bit audio inputs and outputs (video layer and graphics layer 1). Functional Block Diagram The Hi3518E is a new- 16bit 512Mb DDR2 ARM Subsystem Image Subsystem generation IP Camera SoC for civilian use. It has an integrated IVS ENGINE BT1120 ISP, optimized algorithm for ARM926 @440 MHz DDRC (16 KICache/16 KDCache) Output graphics processing before VPSS+TDE. encoding, and an RAW/. ISP BT656 encoder. By using the advanced SD/MMC SDIO. 3A\WDR Input low-power technology and low-power architecture, the SPI NOR Flash I/F.

5 Flash Hi3518E is industry-leading in BUS. the aspects of low bit rate, high RTC picture quality, and low power I2C consumption. The EBOM costs Video Subsystem for the Hi3518E IP Camera MAC PHY MAC SSP 2. H264 BP/MP are significantly reduced by MJPEG/JPEG integrating the DRAM, POR, Encoder GPIOs RTC, and audio CODEC and USB IR. USB Device supporting various sensor levels Host AES/DES/3 DES UART 3 and clock outputs. Similar to Audio IS. 2. other HiSilicon DVR and NVR. PWM 4. SDKs, the Hi3518E SDK allows SAR-ADC rapid mass production and Hi3518E facilitates system layout of IP. cameras, DVRs, and NVRs. Hi3518E IP Camera Solution Encryption Chip PHY. EPHY Reset RAW Date GPIO GPIO DDRC. or ISP GPIO clock MAC. VIU0. Sensor clock SDIO SD or TFcard Sensor I2C or SPI.

6 Sensor Reset DRAM USB Host Wifi GPIO 512Mb Flash triger Audio AI PWM. Codec IR-CUT GPIO. Hi3518E . Infrared GPIO. LED Status GPIO LED. Button RTC. battery ADC SFC Uart 0 Uart 1 GPIO GPIO GPIO. OSC Crystal Temperatu re RS232 RS4 85. One Photo Nor Alarm Alarm Debug PTZ out Push resistance Flash in reset Copyright Hisilicon Technologies Co., Ltd. 2014. All Rights Reversed. THIS DOCUMENT IS INTENDED FOR INFORMATION PURPOSES ONLY. DOES NOT CONSTITUTE ANY KIND OF WARRANTIES.