Hi3531A H.264 CODEC Processor Brief Data Sheet

1 Hi3531A . Hi3531A CODEC Processor Brief data Sheet Key Specifications interface Two 8-bit interfaces that can form a 16-bit interface Processor Core 108 MHz/144 MHz 4xD1/960H TDM inputs for each 8- z Dual-core ARM Cortex GHz bit interface (32xD1/32x960H real-time video inputs in 32 KB L1 I-cache, 32 KB L1 D-cache total). 256 KB L2 cache 144 MHz 2x720p TDM inputs for each 8-bit NEON and FPU interface (16x720p@30 fps real-time video inputs in Video Encoding/Decoding Protocols total). 4x720p TDM inputs through MHz dual-edge z baseline/main/high profile sampling or 297 MHz single-edge sampling for each 8- z MJPEG/JPEG baseline bit interface (32x720p@30 fps real-time video inputs in Video Encoding/Decoding total). z multi-stream encoding and decoding MHz inputs in Y/C interleaved mode for 8x1080p@30 fps encoding+8xCIF@30 fps each 8-bit interface (8x1080p@30 fps real-time video encoding+4x1080p@30 fps inputs in total).

2 Decoding+8x1080p@2 fps JPEG encoding 2x1080p TDM inputs through MHz dual-edge 16x720p@30 fps encoding+16xCIF@30 fps sampling or 297 MHz single-edge sampling for each 8- encoding+8x720p@30 fps bit interface (16x1080p@30 fps real-time video inputs decoding+16x720p@2 fps JPEG encoding in total). 32x960H@30 fps encoding+32xCIF@30 fps MHz standard mode for the 16-bit encoding+8x960H@30 fps interface (4x1080p@60 fps real-time video inputs in decoding+32x960H@2 fps JPEG encoding total). 32xD1@30 fps encoding+32xCIF@30 fps One 3840 x 2160@30 fps input through MHz encoding+16xD1@30 fps decoding+32xD1@2 dual-edge sampling or 297 MHz single-edge sampling fps JPEG encoding for the 16-bit video cascade input interface z CBR or VBR, ranging from 16 kbit/s to 40 Mbit/s z VO interfaces z Fixed QP One HDMI output interface with the maximum z Encoding frame rate ranging from 1/16 fps to full frame output of 3840 x 2160@30 fps rate One VGA HD output interface with the maximum z ROI encoding output of 2560 x 1600@60 fps z Color-to-gray encoding One HD output interface with the maximum Intelligent Video Analysis output of 1080p@60 fps z Integrated IVE, supporting various intelligent analysis One cascade output interface with the applications such as motion detection, perimeter defense.

3 Maximum output of 1080p@60 fps and video diagnosis Two independent HD output channels (DHD0 and DHD1), output over any HD interface (HDMI, VGA, or Video and Graphics Processing Cascade Interface ). z Video pre- and post-processing, including deinterlacing, 64-picture output for DHD0, maximum output of 3840. sharpening, 3D denoising, DCI, and demosaic x 2160@30 fps z Anti-flicker for output videos and graphics 64-picture output for DHD1, maximum output of z 1/15x to 16x video scaling 1080p@60 fps z 1/2x to 2x graphics scaling One CVBS SD output interface z Four Cover regions Three full-screen GUI graphics layers in ARGB1555 or z OSD overlaying of eight regions ARGB8888 format for two HD channels and one SD. Audio Encoding/Decoding channel z ADPCM, , and hardware audio encoding Two hardware cursor layers in ARGB1555 or z Software audio encoding and decoding complying with ARGB8888 format (configurable) with the maximum multiple protocols resolution of 256 x 256.

4 Security Engine Audio Interfaces z AES, DES, and 3 DES algorithms implemented by using z Five unidirectional I2S/PCM interfaces hardware Three input interfaces, supporting 20 multiplexed inputs Video Interfaces Two output interfaces, supporting the dual-channel output z VI interfaces 16-bit audio inputs and outputs Eight 8-bit interfaces and one 16-bit video cascade HiSilicon Proprietary and Confidential Issue 03 (2016-02-29) 3. Copyright HiSilicon Technologies Co., Ltd Hi3531A . Hi3531A CODEC Processor Brief data Sheet Ethernet Ports NOR flash). z One gigabit Ethernet port Maximum capacity of 4 Gbits for each CS (only for the RGMII, RMII, and MII modes SPI NAND flash). 10/100 Mbit/s half-duplex or full-duplex 2 KB/4 KB page size (only for the SPI NAND flash). 1000 Mbit/s full-duplex 8-bit/1 KB or 24-bit/1 KB ECC (only for the SPI.

5 TSO for reducing the CPU usage NAND flash). z Embedded 4 KB BOOTROM and 64 KB SRAM. Peripheral Interfaces z Four SATA multiplexed interfaces RTC with an Independent Power Supply Configurable four SATA interfaces, two 2-lane PCIe z Independent battery for supplying power to the RTC. interfaces, two SATA interfaces+two 1-lane PCIe Configurable Boot Modes interfaces, or one USB interface+two SATA z Booting from the BOOTROM. interfaces+one 1-lane PCIe interface z Booting from the SPI NOR flash RC and EP supported as the PCIe interface z Booting from the SPI NAND flash eSATA and PM supported as the SATA interface z Booting from the NAND flash USB host and hub supported as the USB interface z Booting the slave chip over the PCIe interface z Two USB host interfaces, supporting the hub SDK. z Four UART interfaces (including two 4-wire interfaces).

6 Z One SPI, supporting four CSs z Linux SDK. z One IR interface z Audio encoding and decoding libraries complying with z Two I2C interface multiple protocols High-performance PC decoding library z Multiple GPIO interfaces Memory Interfaces Physical Specifications z Two 32-bit DDR3/DDR3L SDRAM interfaces z Power consumption Typical power consumption of 5 W. Maximum frequency of 866 MHz Multi-level power consumption control Dual channels ODT. z Operating voltages V core voltage Maximum capacity of 3 GB. V CPU voltage z NAND flash interface V I/O voltage 8-bit NAND flash V DDR3 SDRAM interface voltage Two CSs SLC or MLC. z Package RoHS, EDHS-PBGA. 8-/24-/40-/64-bit ECC (based on 1 KB data block). Ball pitch of mm ( in.). z SPI NOR/NAND flash interface Body size of 27 mm x 27 mm ( in. x in.). 1-/2-/4-bit SPI NOR/NAND flash Two CSs, connected to different types of flash z Operating temperature ranging from 0 C (32 F) to 70 C.

7 Memories (158 F). Maximum capacity of 32 MB for each CS (only for the HiSilicon Proprietary and Confidential Issue 03 (2016-02-29) 4. Copyright HiSilicon Technologies Co., Ltd Hi3531A . Hi3531A CODEC Processor Brief data Sheet Functional Block Diagram ARM Subsystem Image Subsystem 64bit DDR3 VPSS/VGS HDMI/VGA/. DDRCx1 CVBS/. @866 MHz A9 dual out 32KB/32KB L1 Cache TDE. USB PORT 256KB L2 Cache PCIe 2x/ IVS SATA Hard ENGINE input disk PCIe switch BUS. USB USB PORT RTC. Host x2. Video CODEC I2C. GMACx1 GE PHY. (TSO) MJPEG/JPEG SRAM. SPI BootROM. NOR/NAND SFC. Flash IR. VOIE. AES/DES/. NAND Flash NANDC UARTx4. 3 DES. DMAC PMC. Video AD SSP. GPIOs Audio CODEC I2S. Hi3531A . The Hi3531A is a professional SoC targeted for multi-channel HD (1080p/720p) or SD (D1/960H) DVRs. The Hi3531A provides an embedded dual-core ARM A9 Processor , a high-performance video encoding/decoding engine, a high-performance video/graphics processing engine integrated with various complicated graphics processing algorithms, HDMI/VGA HD outputs, and various peripheral interfaces.)

8 These features enable the Hi3531A to provide high-performance, high-picture-quality, and low-cost analog HD/SDI solutions for customers' products while greatly reducing the eBOM cost. DVRs (Each with a Hi3531A ). 8x1080p DVR. z 8x1080p@30 fps encoding+8xCIF@30 fps encoding+4x1080p@30 fps decoding+8x1080p@2 fps JPEG. encoding z HDMI 4K x 2K@30 fps output 16x720p DVR. z 16x720p@30 fps encoding+16xCIF@30 fps encoding+8x720p@30 fps decoding+16x720p@2 fps JPEG. encoding HiSilicon Proprietary and Confidential Issue 03 (2016-02-29) 5. Copyright HiSilicon Technologies Co., Ltd Hi3531A . Hi3531A CODEC Processor Brief data Sheet z HDMI 4K x 2K@30 fps output 32x960H DVR. z 32x960H@30 fps encoding+32xCIF@30 fps encoding+8x960H@30 fps decoding+32x960H@2 fps JPEG. encoding z HDMI 4K x 2K@30 fps output+CVBS output 32xD1 DVR. z 32xD1@30 fps encoding+32xCIF@30 fps encoding+16xD1@30 fps decoding+32xD1@2 fps JPEG.

9 Encoding z HDMI 4K x 2K@30 fps output+CVBS output SATA SATA SATA. HDD HDD HDD. LCD monitor LCD monitor TV. SATA SATA. port multiplier port multiplier HDMI VGA CVBS SATA SATA. Flash SFC/NANDC. USB host Hi3531A . DDR3 DDR Ctrl USB host GE PHY GMAC. GMAC VI0 VI1. VI0 VI1 VI6 VI7 I2S0 I2S1 I2S2 I2S3. LAN/WAN. 32/16 channels, audio/video decoding HiSilicon Proprietary and Confidential Issue 03 (2016-02-29) 6. Copyright HiSilicon Technologies Co., Lt