High-Speed Layout Guidelines for Signal Conditioners and ...

1 1 SLLA414 August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand USBHubsApplicationReportSLLA414 August2018 High-SpeedLayoutGuidelinesfor SignalConditionersand moderninterfacefrequenciesscalehigher,ca remustbe takenin the printedcircuitboard(PCB)layoutphaseof a designto ensurea highspeedlayoutsguidelinesrelatingto USB,USBHubs,HDMI,DisplayPort,PCIeand of Figures1 Intervs. IntraPair CapacitorAcrossa AC Via Via SpacingNextto SpacingNextto Clockor a of August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand USBHubs2 PossibleBoardStack-upon a a trademarksare the propertyof August2018 SubmitDocumentationFeedbackCopyright 2018.

2 TexasInstrumentsIncorporatedHigh-SpeedLa youtGuidelinesfor SignalConditionersand applicationreportcan help systemdesignersimplementbest practicesand understandPCBlayoutoptionswhenusingdiffe renthigh documentis intendedfor audiencesfamiliarwithPCBmanufacturing,la yout,and primaryconcernwhendesigninga systemis accommodatingand high-speedsignalsare mostlikelyto impactor be impactedby othersignals,they mustbe laid out early(preferablyfirst)in the PCBdesignprocessto ensurethat prescribedroutingrulescan be differentialdatapairSSTXP/N,SSRXP/NSuper SpeeddifferentialdatapairSATA_RXP/N,SATA _TXP/NSerialATA(SATA)differentialdatapai rPCIe_RXP/N,PCIe_TXP/NPCI-Express(PCIe)d ifferentialdatapairHDMI_CLK+/-High-Defin itionMultimediaInterface(HDMI)differenti alclockpair,positiveor negativeHDMI_Data+/-High-DefinitionMulti mediaInterface(HDMI)

3 Differentialdatapair,positiveor negativeDP_Lane#+/-DisplayPortdifferenti aldatapair,Lane0 through3, positiveor negative2 ProtocolSpecificLayoutguidelinesThereare manydifferencesin the variousHighspeedstandardsthat needto be takeninto accountwhendesigningthe layoutof a data-rates/frequency,ACcouplingcapacitor s,inter-pairskew,intra-pairskewand standardvaluesforthe differenthigh followingvaluesand supposeto be guidelinesare not speed :750 KHz ( Mbps)Full speed :6 MHz(12 Mbps)HighSpeed:240 MHz(480 Mbps)AC CouplingCapacitorsNo AC CapacitorsallowedPolarityReversalNot allowedTraceImpedance90 15%differential,45 15%singleendedMax CableLength5 August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand Ghz (5 Gbps)Superspeed+:5 Ghz (10 Gbps)AC CouplingCapacitorsAC capacitorsrequiredon the TX datalane.

4 (Optionalon the RXdatalane)PolarityReversalallowedon SSTXand SSRXMax Intra-PairSkew15 ps/m(TI recommends5 mils)Max Inter-PairSkewN/ATraceImpedance90 15%differential;45 15%singleendedMax CableLength3 :HDMI_CLK:up to 340 :HDMI_Data:upto :HDMI_CLK:up to 150 :HDMI_Data:to up 3 GhzAC CouplingCapacitorsNo AC capacitorsallowedPolarityReversalNot allowedMax Intra-PairSkewfor * TbitMax Inter-PairSkewfor * TcharacterTraceImpedance100 15%differential;50 15% : GHz( Gbps) : ( Gbps) : ( Gbps)AC CouplingCapacitorsAC capacitorsrequiredPolarityReversalNo built in supportMax Intra-PairSkew20 ps (~TI recommendsabout5 mils)TraceImpedance100 10%differential.

5 50 15% August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand 1: ( Gbps)PCIeGen 2: GHz(5 Gbps)PCIeGen 3: 4 GHz(8 Gbps)PCIeGen 4: 8 GHz(16 Gbps)AC CouplingCapacitorsAC capacitorsrequiredPolarityReversalallowe dMax Intra-PairSkew5 milsMax Inter-PairSkewNo Inter-pairspecificationTraceImpedancePCI eGen 1&2 :100 5% differential;50 5% singleendedPCIeGen 3&4 :85 5% differential; 5% :750 MHz( Gbps)SATA- GHz(3 Gbps)SATA-III:3 Gbps(6 Gbps)AC CouplingCapacitorsAC capacitorsrequiredMax Intra-PairSkew5 milsPolarityReversalNot allowedTraceImpedance100 10%differential.

6 50 10% August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand high speedsignalstraceimpedanceneedsto designedas to minimizethe reflectionsin two typesof traceimpedancethat needto be takeninto considerationwhendesigninghigh the traceimpedancewith referenceto the impedancebetweentwo differentialpair Highspeedprotocolthat is beingdesignedfor determineswhatthe singleand differentialtraceImpedancethe tracesneedto meetas well as the tolerancefor the impedance( 15%).

7 To havedesignsbe robustfromPCBmanufacturingerrorsand defectsdesignthe tracesimpedancebe as closetothe geometryof the traces,the permittivityof the PCBmaterialand the layerssurroundingthe traceall impactthe impedanceof the manytoolsavailableto calculatethe traceimpedanceon high havea preferredtool that PCBdesignerscan use to calculatethe Impedancebut thereare also with all high-speedsignals,keeptotal tracelengthfor signalpairsto a maximumtrace/cablelengthwhichis specifiedin the etch lengthsof the relevantdifferentialpair the termusedto definethedifferencebetweenthe etch lengthof the + and - lane of a usedtodescribethe differencebetweenthe etch lengthsof a differentialpair fromanotherdifferentialpair of etch lengthof the differentialpair groupsdo not needto examplethe etchlengthsof TX and RX do not needto also standardsthat do not havea Inter-pair skewrequirementbecausethe

8 Differentlanesdo not haveto be the the high-speedsignals,add serpentineroutingto matchthe lengthsas closeto themismatchedendsas possibleReferto Intervs. IntraPair August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand USBHubsFigure2. SerpentineTraceGeometryUse the aboverecommendationsfor the examplethe widthof thetrace(W)is 6 mils and the distancebetweenthe differentialpair(A)is 8 the widthofthe serpentine(B)is at least16 mils and the lengthof C is at least18 electricalcircuitmustalwaysbe a closedloop , the returncurrenttakesthe way backwith the lowestresistancefor DC ReturnPathAt higherfrequencies,the returncurrentflowsalongthe lowestimpedancepath.

9 This lowestimpedancepathis usuallythe referenceplaneadjacentto the signalsee the this reasonit is alwaysbest to havea groundplaneor powerplaneon the layeraboveor belowa returnpathhelpsto reduceimpedancechangesand decreaseEMI August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand USBHubsThe red arrowsare the signalpathand the blue arrowsare the routedovera solidGNDreferenceplaneand not acrossa planesplit or avoid in the doesnot recommendhigh-speedsignalreferencesto powerplanesunlessit is red arrowsare the signalpathand the blue arrowsare the RoutingAcrossa SplitPlaneRoutingacrossa planesplit or a void in the referenceplaneforcesreturnhigh-frequency currentto flowaroundthe split or showsthat

10 The returnpathmusttake a longerroutethanthe signalpaththis can resultin the followingconditions: Excessradiatedemissionsfroman unbalancedcurrentflow Delaysin signalpropagationdelaysdue to August2018 SubmitDocumentationFeedbackCopyright 2018,TexasInstrumentsIncorporatedHigh-Sp eedLayoutGuidelinesfor SignalConditionersand USBHubs Interferencewith adjacentsignals Degradedsignalintegrity(thatis, morejitter and reducedsignalamplitude)If routingovera plane-splitis completelyunavoidable,placestitchingcapa citorsacrossthe split to providea returnpathfor the currentloop areaandany impedancediscontinuitycreatedby crossingthe 1 F or lowerandplacedas closeas possibleto the red arrowsare the signalpathand the blue arrowsare the AC CapacitorAcrossa SplitPlaneWhenplanninga PCBstackup,ensurethat planesthat