Transcription of HSPICE Signal Integrity User Guide
1 HSPICE Signal Integrity user GuideVersion , September 2005iiHSPICE Signal Integrity user Notice and Proprietary InformationCopyright 2005 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc.
2 , or as expressly provided by the license to Copy DocumentationThe license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of _____ and its employees.
3 This is copy number _____. Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader s responsibility to determine the applicable regulations and to comply with , INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR Trademarks ( )
4 Synopsys, AMPS, Arcadia, C Level Design, C2 HDL, C2V, C2 VHDL, Cadabra, Calaveras Algorithm, CATS, CRITIC, CSim, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSIM, HSPICE , Hypermodel, iN-Phase, in-Sync, Leda, MAST, Meta, Meta-Software, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, RapidScript, Saber, SiVL, SNUG, SolvNet, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, ( )
5 Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, Direct RTL, Direct Silicon Access, Discovery, DW8051, DWPCI, Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Galaxy, Gatran, HANEX, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSIM plus, HSPICE -Link, iN-Tandem, Integrator.
6 Interactive Waveform Viewer, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Library Compiler, Libra-Visa, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDL lint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, ProGen, Prospector, Protocol Compiler, PSMGen, Raphael, Raphael-NES, RoadRunner, RTL Analyzer, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT.
7 Taurus, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True- HSPICE , TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Marks (SM)MAP-in, SVP Caf , and TAP-in are service marks of Synopsys, is a trademark of the Open SystemC Initiative and is used under and AMBA are registered trademarks of ARM other product or company names may be trademarks of their respective owners.
8 Printed in the Signal Integrity user Guide , Signal Integrity user This Manual..xiThe HSPICE Documentation Set..xiiSearching Across the HSPICE Documentation Set..xiiiOther Related Publications ..xivConventions ..xivCustomer Support ..1 Preparing for Simulation ..1 Signal Integrity Problems ..3 Analog Side of Digital Logic ..3 Optimizing TDR Packaging ..8 Using TDR in Simulation ..8 TDR Optimization Procedure ..10 Simulating Circuits with Signetics Drivers ..13 Simulating Circuits with Xilinx FPGAs.
9 16 Syntax for IOB (xil_iob) and IOB4 (xil_iob4) ..17 Ground-Bounce Simulation ..18 Coupled Line Noise .. Parameter Modeling Using the S Element..25S Parameter Model ..25 Using the Scattering Parameter Element ..26S Element Syntax..27S Model Syntax ..32S Element Data File Model Examples ..35S Element Noise Model ..38ivHSPICE Signal Integrity user Noise Parameter Support in Touchstone Files ..38 Input Interface ..39 Output Interface ..40 Notifications and Limitations..41 Multiport Noise Model for Passive Systems.
10 41 Input Interface ..41 Output Interface ..43 Notifications and Limitations ..43 Mixed-Mode S Parameters ..44 Relating Voltage and Current Waves to Nodal Waves ..44 Characterizing Differential Data Transfer Systems..46 Deriving a Simpler Set of Voltage and Current Pairs ..46 Using the Mixed-Mode S Parameters (S Element) ..48 Mixed-Mode S Parameter Netlist Examples ..50 Small- Signal Parameter Data-Table Model ..50SP Model Syntax .. Coupled Transmission LinesUsing the W Element.. 61 Equations and Parameters.
