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Integrated High Power Solutions for Xilinx FPGAs

Integrated , high Power Solutions for Xilinx FPGAs Modern, high performance, FPGA-based systems require an increasing number of dedicated rails supplying core, I/O, memory, PLL, and precision analog voltages. Typical FPGA-based systems today make use of standalone switching regulators and LDOs, but as board area continues to shrink as end product form factors shrink, this complicates the task of designing more efficient Power management Solutions for powering FPGAs . Combining multiple switching regulators and LDOs into a single package enables very small, flexible, highly efficient Power management Solutions for powering FPGAs and precision analog components with the highest system reliability.

analog.com/multioutput-regulators Integrated, High Power . Solutions for Xilinx FPGAs. Modern, high performance, FPGA-based systems require an increasing number of dedicated rails supplying core, I/O, memory,

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Transcription of Integrated High Power Solutions for Xilinx FPGAs

1 Integrated , high Power Solutions for Xilinx FPGAs Modern, high performance, FPGA-based systems require an increasing number of dedicated rails supplying core, I/O, memory, PLL, and precision analog voltages. Typical FPGA-based systems today make use of standalone switching regulators and LDOs, but as board area continues to shrink as end product form factors shrink, this complicates the task of designing more efficient Power management Solutions for powering FPGAs . Combining multiple switching regulators and LDOs into a single package enables very small, flexible, highly efficient Power management Solutions for powering FPGAs and precision analog components with the highest system reliability.

2 Ultrasmall 12 V/5 V Quad Buck in LFCSP ADP5054 Solution Size Only 41 mm 20 mm 5V/12V. ADP5054. 6A BUCK. VCCINT. 6A BUCK. BUCK VCCAUX. BUCK VCCO_1V2. Xilinx . UltraScale . ADP5054 KINTEX/VIRTEX. 6A BUCK VCCO_1V5. 6A BUCK MGTAVCC. BUCK MGTAVTT. BUCK VCCO_3V3. Wide Range of Switching Frequency Resistor Programmable Current Limit Fixed and Adjustable Output Voltages Operation (250 kHz to 2 MHz) on Buck 1 and Buck 2 (6 A, 4 A, 2 A ). Frequency Synchronization Parallel Operation on Buck 1 and Simple Power Supply Sequencing Input or Output Buck 2, and Buck 3 and Buck 4. ADP5054 Supply for Xilinx UltraScale Kintex/Virtex INPUT SAMPLE: ADP5054 #1 Xilinx UltraScale TO KINTEX/VIRTEX.

3 PVIN1A. FB1 R1. C1 PVIN1B. 10 F BST1. R2. PVIN1C. SW1A. BUCK 1 C2. COMP1 L1 = H TO 6A SW1B. VCCINT. C3 R3 VREG D1. EN1 SW1C. VREG Q1 C4 C5 C6. DL1 G1 100 F 100 F 100 F VCCBRAM. S1. CFG12 VREG PGND R4. VREG R8 VCCINT_IO. DL2 G2. S2. PVIN2A. SW2A Q2. C7 PVIN2B. SW2B D2 L2 = H. 10 F. BUCK 2. PVIN2C. 6A SW2C. C8. COMP2 BST2. EN2 BUCK 1/BUCK 2 INTERLEAVED. FB2 CONNECTION UP TO 12A. PVIN3 BST3. VAUX VCCBATT. C9 C10. L3 = H. 10 F SW3 COMP3 BUCK 3 VCCAUX. VCCINT. C11 R11 R9 C12. EN3 FB3 VCCAUX_IO. 47 F. VREG PGND3 R10. VCCO_1V8. CFG34. BST4. PVIN4 C14. SW4 L4 = H C13 VCCO_1V2. 10 F BUCK 4. COMP4 FB4 R12. C16. VCCAUX C15 R14 47 F. R13. PGND4. EN4. VREG. PWRGD R16. VDD PG GPO1.

4 VREG INT SYNC/MODE. REG. OSC RT. C17 C18 R17. VREG. EXP PAD. R18. ADP5054 #2. VREG. PWRGD R19. VDD PG GPO2. VREG INT SYNC/MODE. REG. OSC RT. C19 C20 R20. PVIN1A. FB1 R21. C21 PVIN1B. BST1 VTT. 10 F R22. PVIN1C. SW1A VTT DRV EXTERNAL DDR3. BUCK 1 C22. COMP1 L5 = H VDDR. VCCAUX 6A SW1B. C23 R23 D1. EN1 SW1C. VREG Q1 C24 C25. DL1 G1 100 F 100 F. S1 VCCO_1V5. CFG12 VREG PGND R24. VREG R28. DL2 G2. S2. PVIN2A Q2. SW2A. C26 PVIN2B. SW2B D2 L6 = H 10 F BUCK 2 VCCO_1. MGTAVCC. PVIN2C 6A SW2C R25. C28. COMP2 BST2 C29 C30. R26 100 F 100 F. C27 R27. EN2 FB2. VREG. PVIN3. BST3. C31 C32. 10 F SW3 L7 = H COMP3 VCCAUX_IO. BUCK 3 MGTAVTTRCAL. MGTAVCC. C33 R31 EN3 FB3 R29 C34 VCCAUX.

5 MGTAVTT. 47 F. VREG PGND3 R30. CFG34. ADP121 VMGTVCCAUX. BST4. PVIN4 C36. L8 = H. SW4 C35 MGTAVCC. VCCO_3V3. 10 F BUCK 4. COMP4 FB4 R32. VCCAUX C38. C37 R34 47 F. EN4 PGND4 R33. EXP PAD. Part Number of Max Output Switching Frequency Reset Trip Min Reset Typ Watchdog Price 1k VIN (V) VOUT (V) I2C Package Number Outputs Current (A) Range Threshold (V) Timeout (ms) Timeout (ms) List ($ ). 2 4 A1 bucks to VIN to 15 250 kHz to MHz ADP5050 2 A bucks to VIN Yes 48-lead LFCSP 1 200 mA LDO to to 200 mA . 2 4 A1 bucks to VIN 1, 20, 140, , 102, 1600, ADP5051 to 15 250 kHz to MHz Yes (adj) 48-lead LFCSP 2 A bucks to VIN 1120 25,600. 2 4 A1 bucks to VIN to 15 250 kHz to MHz ADP5052 2 A bucks to VIN 48-lead LFCSP 1 200 mA LDO to to 200 mA.

6 2 4 A1 bucks to VIN 1, 20, 140, , 102, 1600, ADP5053 to 15 250 kHz to MHz (adj) 48-lead LFCSP 2 A bucks to VIN 1120 25,600. 2 6 A2 bucks to VIN 6/4/22. ADP5054 to 250 kHz to 2 MHz 48-lead LFCSP 2 A bucks to VIN 1. Resistor programmable current limit (4 A, A, or A). 2. Resistor programmable current limit (6 A, 4 A, or 2 A). 2 | Integrated , high Power Solutions for Xilinx FPGAs Xilinx Power Estimator (XPE) Use Cases for Xilinx UltraScale Kintex/Virtex Bill of Materials for the ADP5054 Powering Xilinx UltraScale Kintex/Virtex Reference Quantity Value Part Number Vendor Footprint (mm) Notes U1, U2 2 4-channel micro PMU ADP5054 ACPZ ADI QFN. C17, C18, C19, C20 4 1 F, X5R, V GRM155R60J105KE19D Murata 0402.

7 C2, C8, C10, C14, C22, C28, C32, 8 F, X5R, 16 V GRM155R61C104KA88D Murata 0402. C36. C1, C7, C9, C13, C21, C26, C31, C35 8 10 F, X5R, 25 V GRM219R61E106KA12 Murata 0805. C4, C5, C6, C24, C25 5 100 F, X5R, V GRM31CR60J107ME39 Murata 1206. C12, C16, C29, C30, 6 47 F, X5R, V GRM21BR60J476ME15 Murata 0805. C34, C38. C3, C11, C15,C23, C27, C33, C37 7 nF, X5R, 25 V GRM155R61E222KA01D Murata 0402. Dual N-FETs, 20 V, 25 A, 16 m Si7232DN Vishay QFN. Q1(Q2), Q3(Q4) 2. Dual N-FETs, 30 V, 10 A, 20 m IRFHM8364 IR QFN. H, 22 A, m XAL6030-122ME Coilcraft L1, L2, L5, L6 4. H, A, 16 m NRS6045-1R3 NMGK Taiyo Yuden H, A, 57 m XFL4020-472ME Coilcraft L3, L4, L7, L8 4. H, A, 70 m NRS4018T-4R7 MDGJ Taiyo Yuden R17, R20 2 k , resistor, 1% Various 0402.

8 R4, R8, R24, R28 4 22 k , resistor, 5% Various 0402. R1, R2, R3, R9, R10, R11, R12, R13, Values depend on output R14, R21, R22, R23, R25, R26, R27, 21 Resistor, 1% Various 0402. voltage setting R29, R30, R31, R32, R33, R34. R16, R18 2 10 k , resistor, 5% Various 0402. Simplified Application Diagram for the ADP5054 Powering Xilinx UltraScale Kintex/Virtex VIN = TO BUCK 1. VCCINT AND VCCBRAM. BUCK 2. BUCK 3 VCCAUX AND VCCBATT. ADP5054. Xilinx UltraScale QUAD BUCK. (6A, 6A, , ) KINTEX/VIRTEX. BUCK 4 VCCO_1V2. BUCK 2 VCCO_1V5. BUCK 3 MGTAVCC. BUCK 4 MGTAVTT. ADP5054. QUAD BUCK. (6A, 6A, , ). BUCK 1 VCCO_xx MEMORY. DDR2. | 3. ADP5050 Supply for Xilinx Zynq INPUT SAMPLE: ADP5054.

9 TO PVIN1A Xilinx ZYNQ. FB1 R1. C1 PVIN1B. 10 F BST1. R2. PVIN1C. SW1A. BUCK 1 C2. COMP1 L1 = 1 H TO 6A SW1B. VCCINT. C3 R3 D1. EN1 SW1C. ON OFF C4 C24 VCCPINT. Q1. VREG DL1 G1 47 F 47 F. S1 VCCBRAM. CFG12 VREG PGND R4. VREG R8. DL2 G2. S2. PVIN2A Q2 VIO. SW2A C5 PVIN2B D2 L2 = H. 10 F SW2B BUCK 2 VCCO_DDR. PVIN2C SW2C. 6A R5. COMP2 C6. BST2 C8 VDDR. R6 47 F. C7 R7 EN2. FB2 EXTERNAL DDR2/DDR3. ON OFF VTT DRV. PVIN3. BST3. C9 VAUX VTT. 10 F C10. L3 = H. SW3 VCCAUX. COMP3. BUCK 3. C11 R11 R9 C12 VCCPAUX. EN3 FB3. ON OFF 47 F. VREG PGND3 R10. VCCPO_MIO1. CFG34 VCCBATT. BST4. VCCADC. PVIN4 C14. SW4 L4 = H C13. VCCO_xx 10 F. BUCK 4. COMP4 R12 VCCPO_MIO0. FB4 C15. C16 R14 47 F.

10 EN4 R13. PGND4. ON OFF. VREG. PWRGD R16. VDD PG GPO1. VREG INT SYNC/MODE. REG GPO2. OSC RT. C20 C19 R21. ADP223. EXP PAD. TO VCCPLL. LDO 1 R25 C21. C23. R22. VREFP. LDO 2 R23 C22. VREFN. R24. ENLD01. ENLD02. Part Number of Max Output Switching Frequency Reset Trip Min Reset Typ Watchdog Price 1k VIN (V) VOUT (V) I2C Package Number Outputs Current (A) Range Threshold (V) Timeout (ms) Timeout (ms) List ($ ). 2 4 A1 bucks to VIN to 15 250 kHz to MHz ADP5050 2 A bucks to VIN Yes 48-lead LFCSP 1 200 mA LDO to to 200 mA . 2 4 A1 bucks to VIN 1, 20, 140, , 102, 1600, ADP5051 to 15 250 kHz to MHz Yes (adj) 48-lead LFCSP 2 A bucks to VIN 1120 25,600. 2 4 A1 bucks to VIN to 15 250 kHz to MHz ADP5052 2 A bucks to VIN 48-lead LFCSP 1 200 mA LDO to to 200 mA.


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