Intel® 5 Series Chipset and Intel® 3400 Series Chipset ...

1 Document Number: 322169-004 intel 5 Series Chipset and intel 3400 series ChipsetDatasheetJanuary 20122 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH intel PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN intel 'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, intel ASSUMES NO LIABILITY WHATSOEVER AND intel DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF intel PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY OTHERWISE AGREED IN WRITING BY intel , THE intel PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE intel PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY may make changes to specifications and product descriptions at any time, without notice.

2 Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained at names featured are used internally within intel to identify products that are in development and not yet publicly announced for release.

3 Customers, licensees and other third parties are not authorized by intel to use code names in advertising, promotion or marketing of any product or services and any such use of intel 's internal code names is at the sole risk of the Virtualization Technology requires a computer system with an enabled intel processor, BIOS, virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit: Active Management Technology requires activation and a system with a corporate network connection, an intel AMT-enabled Chipset , network hardware and software.

4 For notebooks, intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or powered off. Results dependent upon hardware, setup & configuration. For more information, visit High Definition Audio ( intel HD Audio) requires an intel HD Audio enabled system. Consult your PC manufacturer for more information. Sound quality will depend on equipment and actual implementation. For more information about intel HD Audio, refer to original equipment manufacturer must provide TPM functionality, which requires a TPM-supported BIOS. TPM functionality must be initialized and may not be available in all Anti-Theft Technology-PC Protection ( intel AT-p). No computer system can provide absolute security under all conditions.

5 intel Anti-Theft Technology ( intel AT-p) requires the computer system to have an intel AT-enabled Chipset , BIOS, firmware release, software and an intel AT-capable Service Provider/ISV application and service subscription. The detection (triggers), response (actions), and recovery mechanisms only work after the intel AT functionality has been activated and configured. Certain functionality may not be offered by some ISVs or service providers and may not be available in all countries. intel assumes no liability for lost or stolen data and/or systems or any other damages resulting using Client Initiated Remote Access require wired LAN connectivity and may not be available in public hot spots or "click to accept" locations. For more information, refer to and the intel logo are trademarks of intel Corporation in the and other countries.

6 *Other names and brands may be claimed as the property of 2012, intel Corporation. All rights This Manual .. Overview .. 5 Series Chipset and intel 3400 series Chipset SKU Definition .. Documents .. 572 Signal Media Interface (DMI) to Host Controller .. Express* .. Hub Interface .. ATA Interface .. Interface .. Management Processor SMBus System Management Real Time Clock Interface .. Miscellaneous Signals .. intel High Definition Audio Link .. Controller Link .. Serial Peripheral Interface (SPI) .. intel Quiet System Technology and Thermal JTAG Signals .. Clock Signals .. LVDS Signals (Mobile only) .. Analog Display /CRT DAC Signals .. intel Flexible Display Interface (FDI).

7 Digital Display General Purpose I/O Signals .. Manageability Signals .. Power and Ground Signals .. Pin Straps .. Straps .. RTC 973 PCH Pin Pull-Ups and Pull-Downs .. and I/O Signals Planes and Planes for Input Signals .. 1124 System 1195 Functional Bridge (D30:F0) .. Bus Interface .. Bridge As an Initiator .. Reads and Writes .. Reads and Writes .. Reads and Writes .. Cycles .. / Master Aborts .. Master Latency Timer .. Address Cycle (DAC) .. and I/O Decode to PCI .. Error Detection and Generation .. #.. Cycles .. Bridge to Device Number Mapping .. PCI Bus Configuration Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .. Generation .. Support .. from Suspended State.

8 Initiated PM_PME Generation .. # Generation .. Detection .. Button Generation .. Ethernet Controller (B0:D25:F0) .. PCI Express* Bus Layer .. Alignment .. Request Retry Events and Error Reporting .. Parity Error .. with Unsuccessful Completion Status .. Interface .. 5 Series Chipset and intel 3400 series Chipset 82577/82578 PHY Interface .. Power Management .. Up .. LEDs .. Level Reset Support (FLR).. Steps .. Bridge (with System and Management Functions) (D31:F0).. Interface .. Cycle Types .. Field Definition .. Type / Direction (CYCTYPE + DIR) .. Time-Out .. Error # Usage .. Cycles .. Master Power Management .. and PCH Operation (D31:F0) .. Priority.

9 Priority .. Compatibility Mode .. of DMA Transfer Sizes .. Shifting When Programmed for 16-Bit I/O Count by .. Commands .. DMA .. DMA Requests .. DMA Flow of DMA Transfers .. Mode .. Request Field / LDRQ# Rules .. Timers (D31:F0) .. Programming .. from the Interval Timer .. Read .. Latch Command .. 152 Datasheet5 Back Interrupt Controllers (PIC) (D31:F0) .. Interrupts .. Interrupt Sequence .. Command Words (ICWx).. Command Words (OCW).. of Operation .. Nested Mode .. Fully-Nested Mode .. Rotation Mode (Equal Priority Devices) .. Rotation Mode (Specific Priority) .. Mode .. and Level Triggered of Interrupt (EOI) Operations .. End of Interrupt .. End of Interrupt Interrupts.

10 On an Individual Interrupt Request .. Mask Mode .. PCI Interrupts .. Programmable Interrupt Controller (APIC) (D31:F0) .. Mapping .. / PCI Express* Message-Based Interrupts .. Address Remapping .. Interrupt Controller Support .. Serial Interrupt (D31:F0) .. Frame .. Interrupts Not Supported Using SERIRQ .. Frame Format .. Real Time Clock (D31:F0).. RAM Ranges .. Rollover .. Battery-Backed RTC RAM .. Processor Interface (D31:F0) .. Interface Signals and VLW Messages .. # (Mask A20) / A20 GATE .. (Initialization).. # (Numeric Coprocessor Error) .. (Non-Maskable Interrupt) .. Power Good (PROCPWRGD).. Differences .. Legacy Wire (VLW) Power Management (D31:F0) .. and System Power States.