Intel® 6 Series Chipset and Intel® C200 Series Chipset ...

1 intel 6 series chipset and intel C200 Series Chipset Datasheet May 2011. Document Number: 324645-006. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH intel PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR. OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN intel 'S TERMS AND CONDITIONS. OF SALE FOR SUCH PRODUCTS, intel ASSUMES NO LIABILITY WHATSOEVER AND intel DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING. TO SALE AND/OR USE OF intel PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY intel , THE intel PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE.

2 FAILURE OF THE intel PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY O0R DEATH MAY OCCUR. intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

3 Contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by intel . Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics and North American Philips Corporation. intel Anti-Theft Technology: No system can provide absolute security under all conditions. Requires an enabled Chipset , BIOS, firmware and software and a subscription with a capable Service Provider. Consult your system manufacturer and Service Provider for availability and functionality. intel assumes no liability for lost or stolen data and/or systems or any other damages resulting thereof.

4 For more information, visit anti-theft intel High Definition Audio: Requires an intel HD Audio enabled system. Consult your PC manufacturer for more information. Sound quality will depend on equipment and actual implementation. For more information about intel HD Audio, refer to intel vPro Technology is sophisticated and requires setup and activation. Availability of features and results will depend upon the setup and configuration of your hardware, software and IT environment. To learn more visit: intel Active Management Technology ( intel AMT) requires activation and a system with a corporate network connection, an intel AMT-enabled Chipset , network hardware and software. For notebooks, intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or powered off.

5 Results dependent upon hardware, setup & configuration. For more information, visit http://. intel Trusted Execution Technology: No computer system can provide absolute security under all conditions. intel Trusted Execution Technology ( intel TXT) requires a computer system with intel Virtualization Technology, an intel TXT-enabled processor, Chipset , BIOS, Authenticated Code Modules and an intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, intel TXT requires the system to contain a TPM , as defined by the Trusted Computing Group and specific software for some uses. For more information, see intel Virtualization Technology requires a computer system with an enabled intel processor, BIOS, virtual machine monitor (VMM).

6 Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit intel , intel vPro and the intel logo are trademarks of intel Corporation in the and other countries. *Other names and brands may be claimed as the property of others. Copyright 2011, intel Corporation 2 Datasheet Contents 1 Introduction .. 41. About This Manual .. 41. Overview .. 44. Capability 45. intel 6 series chipset and intel C200 Series Chipset SKU Definition .. 51. 2 Signal Description .. 55. Direct Media Interface (DMI) to Host Controller .. 57. PCI Express* .. 57. PCI Interface .. 58. Serial ATA 60. LPC 63. Interrupt Interface.

7 63. USB Interface .. 64. Power Management 65. Processor 69. SMBus 69. System Management 69. Real Time Clock Interface .. 70. Miscellaneous Signals .. 70. intel High Definition Audio Link .. 72. Controller Link .. 73. Serial Peripheral Interface (SPI) .. 73. Thermal Signals .. 73. Testability Signals .. 74. Clock Signals .. 74. LVDS Signals .. 77. Analog Display /VGA DAC Signals .. 78. intel Flexible Display Interface ( intel FDI) .. 78. Digital Display 79. General Purpose I/O Signals .. 82. Manageability Signals .. 86. Power and Ground Signals .. 87. Pin Straps .. 89. External RTC Circuitry .. 92. 3 PCH in S 93. Integrated Pull-Ups and Pull-Downs .. 93. Output and I/O Signals Planes and 95. Power Planes for Input Signals .. 107. 4 PCH and System Clocks.

8 113. Platform Clocking Requirements .. 113. Functional Blocks .. 116. Clock Configuration Access Overview .. 117. Straps Related to Clock Configuration .. 117. 5 Functional Description .. 119. DMI-to-PCI Bridge (D30:F0) .. 119. PCI Bus 119. PCI Bridge As an 120. Memory Reads and Writes .. 120. I/O Reads and Writes .. 120. Configuration Reads and Writes .. 120. Locked Cycles .. 120. Target / Master Aborts .. 120. Secondary Master Latency Timer .. 120. Dual Address Cycle (DAC).. 121. Memory and I/O Decode to PCI .. 121. Parity Error Detection and 121. PCIRST# .. 122. Peer Cycles .. 122. Datasheet 3. PCI-to-PCI Bridge Model .. 122. IDSEL to Device Number 123. Standard PCI Bus Configuration Mechanism .. 123. PCI Legacy Mode .. 123. PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7).

9 124. Interrupt 124. Power Management .. 125. S3/S4/S5 Support .. 125. Resuming from Suspended 125. Device Initiated PM_PME Message .. 125. SMI/SCI Generation .. 126. SERR# 126. Hot-Plug .. 126. Presence 126. Message Generation .. 127. Attention Button Detection .. 127. SMI/SCI Generation .. 127. Gigabit Ethernet Controller (B0:D25:F0) .. 128. GbE PCI Express* Bus Interface .. 130. Transaction 130. Data 130. Configuration Request Retry Status .. 130. Error Events and Error Reporting .. 131. Data Parity Error .. 131. Completion with Unsuccessful Completion 131. Ethernet Interface .. 131. 82579 LAN PHY Interface .. 131. PCI Power 132. Wake Up .. 132. Configurable LEDs .. 134. Function Level Reset Support (FLR) .. 135. FLR Steps .. 135. LPC Bridge (with System and Management Functions) (D31:F0).

10 136. LPC Interface .. 136. LPC Cycle 137. Start Field 137. Cycle Type / Direction (CYCTYPE + DIR) .. 138. Size .. 138. 138. SYNC 139. SYNC Error Indication .. 139. LFRAME# 139. I/O 139. Bus Master Cycles .. 140. LPC Power Management .. 140. Configuration and PCH Implications .. 140. DMA Operation (D31:F0) .. 141. Channel Priority .. 141. Fixed Priority .. 141. Rotating 142. Address Compatibility Mode .. 142. Summary of DMA Transfer 142. Address Shifting When Programmed for 16-Bit I/O Count by Words .. 142. 143. Software 143. LPC DMA .. 144. Asserting DMA 144. Abandoning DMA Requests .. 145. General Flow of DMA 145. Terminal Count .. 145. Verify Mode .. 146. DMA Request 146. SYNC Field / LDRQ# Rules .. 147. 8254 Timers (D31:F0) .. 147. Timer Programming.