Intrinsic Silicon Properties - Michigan State University

1 ECE 410, Prof. A. MasonLecture Notes Silicon Properties Read textbook, section , , Intrinsic Semiconductors undoped ( , not n+ or p+) Silicon has intrinsiccharge carriers electron-hole pairs are created by thermal energy Intrinsic carrier concentration ni= , at room temp. function of temperature: increase or decrease with temp? n = p = ni, in Intrinsic (undoped) material n number of electrons, p number of holes mass-action law, np = ni2 applies to undoped and doped materialECE 410, Prof. A. MasonLecture Notes Silicon Properties doping, adding dopantsto modify material Properties n-type = n+, add elements with extra an electron (arsenic, As, or phosphorus, P), Group V elements nn concentration of electrons in n-type material nn= Ndcm-3, Nd concentration of donoratoms pn concentration of holes in n-type material Ndpn= ni2, using mass-action law always a lot more n than p in n-type material p-type = p+, add elements with an extra hole (boron, B)

2 Pp concentration of holes in p-type material pp= Nacm-3, Na concentration of acceptoratoms np concentration of electrons in p-type material Nanp= ni2, using mass-action law always a lot more p than n in p-type material if both Ndand Napresent, nn= Nd-Na, pp=Na-Nddo example on boardni2= +/p+ defines regionas heavily doped, typically 1016-1018cm-3less highly doped regions generally labeled n/p (without the +)PP++-group Velementionelectronn-type DonorfreecarrierBB++-group IIIelementholep-type AcceptorionfreecarrierECE 410, Prof. A. MasonLecture Notes in Semiconductors doping provides free charge carriers, alters conductivity conductivity, , in semic.

3 W/ carrier densities nand p = q( nn+ pp), q electron charge, q= [Coulombs] mobility[cm2/V-sec], n 1360, p 480 (typical values) in n-type region, nn>> pn q nnn in p-type region, pp>> np q pnp resistivity, = 1/ resistance of an n+ or p+ region R = l , A = wt drift current(flow of charge carriers in presence of an electric field, Ex) n/p drift current density: Jxn = nEx= q nnnEx, Jxp = pEx= q pppEx total drift current densityin x direction Jx = q( nn+ pp) Ex= Exmobility = average velocity per unit electric field n> pelectrons more mobile than holes conductivity of n+ > p+ltwAMobility often assumed constantbut is a function of Temperature and Doping ConcentrationECE 410, Prof.

4 A. MasonLecture Notes Junctions: Intro What is a pn Junction? interface of p-type andn-type semiconductor junction of two materials forms a diode In the ionization of dopantsat material interface Diffusion -movement of charge to regions of lower concentration free carries diffuse out leave behind immobile ions region become depleted offree carriers ions establish an electric field acts against diffusiondonor ion and electron free carrieracceptor ion and hole free carrierp-typehole diffusionhole currentelectron diffusionelectron currentN acceptors/cmA3N

5 Donors/cmD3n-type-+-+-+-+-+-+-+-++-+-+-+ -+-+-+-+-+-+-+-Edepletion regionimmobile acceptor ions(negative-charge)immobile donor ions(positive-charge)electric fieldxpWxn--------++++++++p-typeN acceptors/cmA3N donors/cmD3n-typep-type Si waferpn diodejunctiondepletion regionboundariesdielectricinsulato(oxide )contactto p-sidecontactto n-sidep+n+n well rp-typen-typeECE 410, Prof. A. MasonLecture Notes Junctions: Equilibrium Conditions Depletion Region area at pn interface void of free charges charge neutrality must have equal charge on both sides q A xpNA= q A xnND, A=junction area.

6 Xp, xndepth into p/n side xpNA= xnND depletion region will extend further into the more lightly doped side of the junction Built-in Potential diffusion of carriers leaves behind immobile charged ions ions create an electric field which generates a built-in potential where VT= kT/q = 26mV at room temperatureEdepletion regionimmobile acceptor ions(negative-charge)immobile donor ions(positive-charge)electric fieldxpWxn--------++++++++p-typeN acceptors/cmA3N donors/cmD3n-typeNAND = 20lniDATnNNVECE 410, Prof. A. MasonLecture Notes Junctions.

7 Depletion Width Depletion Widthuse Poisson s equation & charge neutrality W = xp+ xn where VRis applied reverse bias One-sided Step Junction if NA>>ND(p+n diode) most of junction on n-side if ND>>NA (n+p diode) most of junction on p-sideEdepletion regionimmobile acceptor ions(negative-charge)immobile donor ions(positive-charge)electric fieldxpWxn--------++++++++p-typeN acceptors/cmA3N donors/cmD3n-typeNAND = 20lniDATnNNV()()2102 ++ =ADADRpNNqNNVx ()()2102 ++ =ADDARnNNqNNVx ()2102 ++ =ADADRNNNNqVW ()2102 + = ARpqNVxW ()2102 + = DRnqNVxW is the permittivity of Si = = KS 0, where 0 = KS= the relative permittivity of siliconECE 410, Prof.

8 A. MasonLecture Notes Junctions - Depletion Capacitance Free carriers are separated by the depletion layer Separation of charge creates junction capacitance Cj= A/d (d = depletion width, W) A is complex to calculate in semiconductor diodes consists of both bottomof the well and side-wallareas Cj is a strong function of biasing must be re-calculated ifbias conditions change CMOS doping is not linear/constant graded junctionapproximation Junction Breakdown if reverse bias is too high (typically > 30V) can get strong reverse current flow() + +=RDADAjVNNNNqAC02112 is the permittivity of Si = 0= applied reverse bias +=01 RjojVCC()2102 + =DADAjoNNNNqAC +=301 RjojVCCECE 410, Prof.

9 A. MasonLecture Notes Forward Bias; VD> 0 acts against built-in potential depletion width reduced diffusion currentsincrease with VD minority carrierdiffusion Reverse Bias; VR= -VD> 0 acts to support built-in potential depletion width increased electric field increased small drift currentflows considered leakage small until VRis too high and breakdown occursDiode Biasing and Current Flow+ V -DVDVf+ V -DIDIDIDpn()1 =TDVVSDeII + ADSNNAI11 ECE 410, Prof. A. MasonLecture Notes Capacitor MOSFETs move charge from drain to source underneath the gate, ifa conductive channel exists under the gate Understanding how and why the conductive channel is produced is important MOSFET capacitormodels the gate/oxide/substrate region source and drain are ignored substrate changes with applied gate voltage Consider an nMOS device Accumulation, VG< 0, (-)ve charge on gate induces (+)ve charge in substrate (+)ve charge accumulate from substrate holes (h+)

10 Depletion, VG> 0 but small creates depletion region in substrate (-)ve charge but no free carriers Inversion, VG> 0 but larger further depletion requires high energy (-)ve charge pulled from Ground electron (e-) free carriers in channelSi substrate = bulkgate oxideGGSDBB gatechannel=p-type Si substratedepletion layerdepletion layerAccumulationDepletionInversionp-typ e Si substratep-type Si substrateV < 0GV > 0GV >> 0 GBBB+ + + + + + ++ + + + + + ++ + + + + + + + + + + + + + + + + + + + +- - - - - - -- - - - - - -- - - - - - -- - - - - - - - - -ECE 410, Prof.