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Introduction to CMOS VLSI Design - University of Notre Dame

1 Introduction toCMOS VLSID esignVLSI Design RulesPeter KoggeUniversity of Notre DameFall 2011, 2012, 2015, 2018 Based on material fromProf. Jay Brockman, Joesph Nahas, University of Notre DameProf. David Harris, Harvey Mudd vlsi DesignDesign RulesSlide 2 Outline Overview Determining Design Rules and Mask Biases Design Rules Circuit Interconnect Layout2 CMOS vlsi DesignDesign RulesSlide 3 layout Overview Minimum dimensions of mask features determine: transistor size and die size hence speed, cost, and power Historical Feature sizef= gate length (in nm) Set by minimum width of polysilicon Other minimum feature sizes tend to be 30 to 50% bigger.

2 Design Rules CMOS VLSI Design Slide 3 Layout Overview Minimum dimensions of mask features determine: – transistor size and die size – hence speed, cost, and power “Historical” Feature size f = gate length (in nm) – Set by minimum width of polysilicon – Other minimum feature sizes tend to be 30 to 50% bigger. Design or Layout Rules: rules ...

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Transcription of Introduction to CMOS VLSI Design - University of Notre Dame

1 1 Introduction toCMOS VLSID esignVLSI Design RulesPeter KoggeUniversity of Notre DameFall 2011, 2012, 2015, 2018 Based on material fromProf. Jay Brockman, Joesph Nahas, University of Notre DameProf. David Harris, Harvey Mudd vlsi DesignDesign RulesSlide 2 Outline Overview Determining Design Rules and Mask Biases Design Rules Circuit Interconnect Layout2 CMOS vlsi DesignDesign RulesSlide 3 layout Overview Minimum dimensions of mask features determine: transistor size and die size hence speed, cost, and power Historical Feature sizef= gate length (in nm) Set by minimum width of polysilicon Other minimum feature sizes tend to be 30 to 50% bigger.

2 Design orLayout Rules: rules for designing masks based on minimum feature sizes Rules often normalized for portability across generationsn+n+p-type bodyWLtoxSiO2 gate o(good insulator, polysilicongateCMOS vlsi DesignWhat Are Typical Rules Length & Width of Transistor gate Separation between 2 wires on same level Width of wires Contact pad for Vias Cross section of Vias Size of Wells .. Design RulesSlide 43 CMOS vlsi DesignDesign RulesSlide 5 Feature Size Feature size improves 30% every 2 years or so 1/ 2 = reduction factor every generation from 1 m (1000 nm) in 1990 to 14 nm in 2015.)

3 10 generations in 20 years 1000, 700, 500, 350, 250, 180, 130, 90, 65, 45, 32, 22, 14, 10 nm01020304050607080902005201020152020202 52030 Feature Size (nm)2013 ITRSXeon DataTop102006 ITRSXeon LineTop10 ProjectionCMOS vlsi DesignDetermining a Design Ruleand a Mask BiasDesign RulesSlide 64 CMOS vlsi DesignDetermining a Design Rule What is the minimum spacing between a poly gate and a contact? What does it depend on? Design RulesSlide 7 GNDVDDYA substrate tapwell tapnMOS transistorpMOS transistor?CMOS vlsi DesignFactors Determining a Design Rule Mask alignment accuracy How accurate is one mask aligned to another mask?

4 Process variation If cutting a hole, how much do sides of the cut vary? If implanting dopants, how much does the width of the diffusion vary? How conservative do you need to be to assure good process yield? 30 to 40 mask levels 5 to 10 process steps per mask levelDesign RulesSlide 85 CMOS vlsi DesignL03 Semiconductor ProcessingSlide 9 Mask Sequence Align each mask to the previous mask1. n-well2. Polysilicon3. n+ active (diffusion)4. p+ active (diffusion)5. Contact6. MetalMetalPolysiliconContactn+ Diffusionp+ Diffusionn wellCMOS vlsi DesignAlignment Marks Alignment Marks: How close can one mask be aligned to another in a m process?

5 Example: Mean: 0 nm Standard Deviation: 50 nm 1 = 50 nm = 84% 2 = 100 nm = 98% 3 = 150 nm = But alignment is not direct Contact aligns to P+active P+active aligns to N+active N+active aligns to poly How much variation is the alignment from Contact to Poly? Design RulesSlide 10 PolyVariationContact6 CMOS vlsi DesignPoly Variation How much does the width of the poly vary with processing? Example: (Again m) Mean (one side) = - 60 nm (undercut) Standard Deviation (one side) = 30 nm 3 = 90 nmDesign RulesSlide 11 SiliconPolyResistUndercut500 nmMask biased to compensatefor mean undercut?

6 CMOS vlsi DesignContact Hole Variation How much does the size of the contact hole vary? Example: Mean = + 50 nm Standard Deviation = 40 nm 3 = 120 nmDesign RulesSlide 12 SiliconSiO2 ResistUndercutSiO2 Resist?600nmMask biased to compensatefor mean undercut7 CMOS vlsi DesignMinimum Oxide Width Cannot have source or drain short to the gate. What is minimum spacing with variation? Example: 200 nmDesign RulesSlide 13 SiliconSiO2 PolyAlSiO2 WMIND iffusion RegionChannelVIAC ontactGATECMOS vlsi DesignDesign Rule Summary Mask Alignment 3 variation is 3 * 150 nm = 260 nm Poly Variation 3 = 90 nm Contact Variation 3 = 120 nm Minimum Contact-to-Poly Breakdown Space 200 nm If we simply sum the minimum and variations: 670 nm Is this the correct value for the rule?

7 What is correct ? Design Rule: nm Why? Design RulesSlide 148 CMOS vlsi DesignHow can the rule be improved? Change alignment sequence. Align poly to n-well Align n+active to poly Align p+active to poly Align contact to poly Align metal to contact Change alignment from t3 to t1 Alignment variation reduces from 260 nm to 150nm Design Rule changes from 500nm to 400nmDesign RulesSlide 15 CMOS vlsi DesignWhat do you do with Biases? layout is done without biases. Biases are added post layout in mask processing. Example: ContactsDesign RulesSlide 16600 nm600 nmLayout600 nm500 nm500 nmMaskContact is shrunk by 50 nm on each side during Mask Making process700 nm9 CMOS vlsi DesignCircuit Interconnect LayoutDesign RulesSlide 17 CMOS vlsi DesignDesign RulesSlide 18 Simplified CMOS Processp silicon substraten welln diffusiongate oxideSiO2 SiO2polysiliconp diffusionNMOSPMOS fieldoxide10 CMOS vlsi DesignDesign RulesSlide 19 Wiring with Metal and Contactsmetal (Al)

8 NMOSPMOS contact cutCMOS vlsi DesignDesign RulesSlide 20 Transistors of Same Type in SeriesNMOSNMOScan t do this with opposite types!connected by shared diffusion11 CMOS vlsi DesignDesign RulesSlide 21 Connecting Poly and Diffusioncan t contact poly to diffusion directly!NMOSNMOSCMOS vlsi DesignThe Book s 65nm ProcessDesign RulesSlide 2212 CMOS vlsi DesignThe Book s 65nm Process- Up to Metal 2 Design RulesSlide 23 CMOS vlsi DesignThe Book s 65nm Process- MetalsDesign RulesSlide 2413 CMOS vlsi Design65nm Design Rules (Page 1) Design RulesSlide 25 RuleDescription65nm(nm)

9 To well at different to well at same Spacing to surround by contact surround by well to active of opposite to poly over field to poly over extension beyond extension beyond of poly to from substrate/well to by poly or of substrate/well to select200 WellActive(diffusion)Poly ( Gate)Select(n or p)CMOS vlsi Design65nm Design Rules (Page 2) Design RulesSlide 26 RuleDescription65nm(nm) , (exact) , by poly or , to , to of poly contact to other , Spacing to active/poly for mult. Spacing of active contact to poly to same layer of , of contact or to metal for lines wider than 10.

10 Spacing to same layer of , ..Overlap of contact or , ..Spacing to metal for lines wider than 10 to of to metal for lines wider than 10 to of to metal for lines wider than 10 , (exact) to via on same , (exact) to via on same , (exact) to via on same layer200 Via7,8 Metal1 Via1 Via2 Metal3 Metal2 Metal8 (topoly or active)14 CMOS vlsi DesignA Simplified Rule System RulesDesign RulesSlide 27 CMOS vlsi Design RulesA simplified, technology generations independent Design rule system: Express rules in terms of = f/2 = mm in mm process Called Lambda rules Lambda rules NOT used in commercial applications Lambda rules need to be very conservative and thus waste space.


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