Introduction to CMOS VLSI Design - UTEP

1 Introduction to cmos vlsi Design Logical Effort cmos vlsi Design Logical Effort Slide 2 Outline q Introduction q Delay in a Logic Gate q Multistage Logic Networks q Choosing the Best Number of Stages q Example q Summary cmos vlsi Design Logical Effort Slide 3 Introduction q Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? q Logical effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries ?

2 ? ? cmos vlsi Design Logical Effort Slide 4 Example q Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben Design the decoder for a register file. q Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors q Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? A[3:0]A[3:0]1632 bits16 words4:16 DecoderRegister FileCMOS vlsi Design Logical Effort Slide 5 Delay in a Logic Gate q Express delays in process-independent unit absdd = = 3RC 12 ps in 180 nm process 40 ps in m process cmos vlsi Design Logical Effort Slide 6 Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components absdd =dfp=+ cmos vlsi Design Logical Effort Slide 7 Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Effort delay f = gh ( stage effort)

3 Again has two components absdd =dpf=+ cmos vlsi Design Logical Effort Slide 8 Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Effort delay f = gh ( stage effort) Again has two components q g: logical effort Measures relative ability of gate to deliver current g 1 for inverter absdd =dfp=+ cmos vlsi Design Logical Effort Slide 9 Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Effort delay f = gh ( stage effort) Again has two components q h: electrical effort = Cout / Cin Ratio of output to input capacitance Sometimes called fanout absdd =dfp=+ cmos vlsi Design Logical Effort Slide 10 Delay in a Logic Gate q Express delays in process-independent unit q Delay has two components q Parasitic delay p Represents delay of gate driving no load Set by internal parasitic capacitance absdd =dpf=+ cmos vlsi Design Logical Effort Slide 11 Delay Plots d = f + p = gh + p Ele c t r ic a l Ef f o r t :h = Cout / CinNormalized Delay.

4 DIn v e r t e r2-inputNA NDg =p =d =g =p =d =0123450123456 cmos vlsi Design Logical Effort Slide 12 Delay Plots d = f + p = gh + p q What about NOR2? Ele c t r ic a l Ef f o r t :h = Cout / CinNormalized Delay: dIn v e r t e r2-inputNA NDg = 1p = 1d = h + 1g = 4/3p = 2d = (4/3)h + 2Ef f o r t De la y : fPa r a s it ic De la y : p0123450123456 cmos vlsi Design Logical Effort Slide 13 Computing Logical Effort q DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. q Measure from delay vs. fanout plots q Or estimate by counting transistor widths AYABYABY1211222244 Cin = 3g = 3/3 Cin = 4g = 4/3 Cin = 5g = 5/3 cmos vlsi Design Logical Effort Slide 14 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 q Logical effort of common gates cmos vlsi Design Logical Effort Slide 15 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 2 3 4 n NOR 2 3 4 n Tristate / mux 2 4 6 8 2n XOR, XNOR 4 6 8 q Parasitic delay of common gates In multiples of pinv ( 1)

5 cmos vlsi Design Logical Effort Slide 16 Example: Ring Oscillator q Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: fosc = cmos vlsi Design Logical Effort Slide 17 Example: Ring Oscillator q Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in m process has frequency of ~ 200 MHz cmos vlsi Design Logical Effort Slide 18 Example: FO4 Inverter q Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = dCMOS vlsi Design Logical Effort Slide 19 Example: FO4 Inverter q Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay.

6 D = 5 dThe FO4 delay is about 200 ps in m process 60 ps in a 180 nm process f/3 ns in an f m process cmos vlsi Design Logical Effort Slide 20 Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort iGg= out-pathin-pathCHC=iiiFfgh== 10xyz20g1 = 1h1 = x/10g2 = 5/3h2 = y/xg3 = 4/3h3 = z/yg4 = 1h4 = 20/zCMOS vlsi Design Logical Effort Slide 21 Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort q Can we write F = GH? iGg= out pathin pathCHC =iiiFfgh== cmos vlsi Design Logical Effort Slide 22 Paths that Branch q No!

7 Consider paths that branch: G = H = GH = h1 = h2 = F = GH? 515159090 cmos vlsi Design Logical Effort Slide 23 Paths that Branch q No! Consider paths that branch: G = 1 H = 90 / 5 = 18 GH = 18 h1 = (15 +15) / 5 = 6 h2 = 90 / 15 = 6 F = g1g2h1h2 = 36 = 2GH 515159090 cmos vlsi Design Logical Effort Slide 24 Branching Effort q Introduce branching effort Accounts for branching between stages in path q Now we compute the path effort F = GBH on pathoff pathon pathCCbC+=iBb= ihBH= Note: cmos vlsi Design Logical Effort Slide 25 Multistage Delays q Path Effort Delay q Path Parasitic Delay q Path Delay FiDf= iPp= iFDdDP==+ cmos vlsi Design Logical Effort Slide 26 Designing Fast Circuits q Delay is smallest when each stage bears same effort q Thus minimum delay of N stage path is q This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes iFDdDP==+ 1 NiifghF==1 NDNFP=+ cmos vlsi Design Logical Effort Slide 27 Gate Sizes q How wide should the gates be for least delay?

8 Q Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. q Check work by verifying input cap spec is met. outiniiCCioutinfgh ggCCf== = cmos vlsi Design Logical Effort Slide 28 Example: 3-stage path q Select gate sizes x and y for least delay from A to B 8xxxyy4545 ABCMOS vlsi Design Logical Effort Slide 29 Example: 3-stage path Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort Parasitic Delay P = Delay D = 8xxxyy4545AB f= cmos vlsi Design Logical Effort Slide 30 Example: 3-stage path Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 Delay D = 3*5 + 7 = 22 = FO4 8xxxyy4545AB3 5fF== cmos vlsi Design Logical Effort Slide 31 Example: 3-stage path q Work backward for sizes y = x = 8xxxyy4545 ABCMOS vlsi Design Logical Effort Slide 32 Example: 3-stage path q Work backward for sizes y = 45 * (5/3) / 5 = 15 x = (15*2) * (5/3) / 5 = 10 P: 4N: 44545 ABP: 4N: 6P: 12N.

9 3 cmos vlsi Design Logical Effort Slide 33 Best Number of Stages q How many stages should a path use? Minimizing number of stages is not always fastest q Example: drive 64-bit datapath with unit inverter D = 111164646464In it ia l Dr iv e rDatapath LoadN:f:D:1234 cmos vlsi Design Logical Effort Slide 34 Best Number of Stages q How many stages should a path use? Minimizing number of stages is not always fastest q Example: drive 64-bit datapath with unit inverter D = NF1/N + P = N(64)1/N + N it ia l Dr iv e rDatapath LoadN:f: tes tCMOS vlsi Design Logical Effort Slide 35 Derivation q Consider adding inverters to end of path How many give least delay?

10 Q Define best stage effort N - n1 Ex t r a I n v e r t e r sLogic Block:n1 S t a g e sPa t h Ef f o r t F()1111 NniinviDNFp Nnp==++ 111ln0 NNNinvDFFFpN = ++= ()1ln 0invp + =1NF = cmos vlsi Design Logical Effort Slide 36 Best Stage Effort q has no closed-form solution q Neglecting parasitics (pinv = 0), we find = (e) q For pinv = 1, solve numerically for = ()1ln 0invp + = cmos vlsi Design Logical Effort Slide 37 Sensitivity Analysis q How sensitive is delay to using exactly the best number of stages? q < < 6 gives delay within 15% of optimal We can be sloppy!